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[Bug]: Search failed with SIGILL: illegal instruction
Is there an existing issue for this?
- [X] I have searched the existing issues
Environment
- Milvus version: 2.3.3
- Deployment mode: cluster
- MQ type: pulsar
- SDK version(e.g. pymilvus v2.0.0rc2): attu v2.3.4
- GPU: no
- Others: Kubernetes helm setup
Current Behavior
Vector Search query
Expected Behavior
No response
Steps To Reproduce
No response
Milvus Log
[2023/12/14 11:14:21.691 +00:00] [INFO] [delegator/distribution.go:294] ["Update readable segment version"] [oldVersion=0] [newVersion=1702552371687878643] [growingSegmentNum=0] [sealedSegmentNum=1]
SIGILL: illegal instruction
PC=0x7fb407333e71 m=19 sigcode=2
signal arrived during cgo execution
instruction bytes: 0xc4 0xe2 0x69 0x99 0x5 0x96 0xe0 0x38 0x0 0xc4 0xc1 0xe2 0x2a 0xce 0xc5 0xf2
[milvus-querynode.log](https://github.com/milvus-io/milvus/files/13672569/milvus-querynode.log)
Anything else?
No response
What is your cpu arch? can you lscpu
to see if it has avx2 instruction set.
/assign @chasingegg /unassign
Flags:
fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts mmx fxsr sse sse2 ss syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts nopl xtopology
tsc_reliable nonstop_tsc cpuid tsc_known_freq pni pclmulqdq monitor ssse3 cx16 pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer aes xsave avx f16c rdrand hypervisor lahf_lm
cpuid_fault pti ssbd ibrs ibpb stibp fsgsbase tsc_adjust smep arat md_clear flush_l1d arch_capabilities
We have two type CPU
- Intel(R) Xeon(R) CPU E5-2696 v2
- Intel(R) Xeon(R) CPU E5-2697 v4
@MikeVL We have fixed it in 2.3.4 for whom does not have avx2 machine, could you try compile milvus from master or 2.3 branch or wait for the coming 2.3.4 release. And avx2 machines should work.
I'll wait for the next release, thanks.
@chasingegg Any updates on this issue? The milestone is being pushed further and further :(
as comments from @chasingegg it was fixed, please retry and if it keeps failing, please attache new log files.
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