acia delay values

[mrdoornbos]

Can you help me understand how you came up with the acia delay values? I've been looking at this for a while and don't quite understand:

acia_delay:
  phy                         ; Save Y Reg
  phx                         ; Save X Reg
  ldy   #6                    ; Get delay value (clock rate in MHz 2 clock cycles)
@minidly:
  ldx   #$68                  ; Seed X reg

What would this look like to delay for a 2400 bps connection?