extmod: Fix compile error for LWIP with SLIP support.

[cajt]

Summary

Fixes a compile error if STM32 port is compiled with:

make BOARD=(..) MICROPY_PY_LWIP=1 MICROPY_PY_LWIP_SLIP=1

Testing

Tested with STM32F4DISC target in hardware, with SLIP link over UART. Ping from Linux host got a proper response.

On STM32F4DISC:

import pyb
import lwip
import network
tim = pyb.Timer(7)
tim.init(freq=20)
tim.callback(lambda t: lwip.callback())
u = pyb.UART(3, 500000, read_buf_len=1550)
sl = lwip.slip(u, "192.168.5.2", "192.168.5.1")

On Host (Linux):

sudo slattach -L -p slip  /dev/ttyUSB0 &
sudo ifconfig sl0 192.168.5.1 pointopoint 192.168.5.2 mtu 1500
ping 192.168.5.2

[github-actions[bot]]

Code size report:

   bare-arm:    +0 +0.000% 
minimal x86:    +0 +0.000% 
   unix x64:    +0 +0.000% standard
      stm32:    +0 +0.000% PYBV10
     mimxrt:    +0 +0.000% TEENSY40
        rp2:    +0 +0.000% RPI_PICO_W
       samd:    +0 +0.000% ADAFRUIT_ITSYBITSY_M4_EXPRESS

[codecov[bot]]

Codecov Report

All modified and coverable lines are covered by tests :white_check_mark:

Project coverage is 98.43%. Comparing base (fd03a05) to head (e9fcc39). Report is 49 commits behind head on master.

Additional details and impacted files

@@           Coverage Diff           @@
##           master   #15740   +/-   ##
=======================================
  Coverage   98.43%   98.43%           
=======================================
  Files         163      163           
  Lines       21295    21295           
=======================================
  Hits        20961    20961           
  Misses        334      334           

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[cajt]

Fixed PR & commit message conventions and sign-off.

[dpgeorge]

Rebased and merged in 65244d291acda865aef60ec3cd7291c2211caeb2