rv8
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michaeljclark
RISC-V simulator for x86-64
The JIT API currently just checks instruction operands and emits the instruction. - Add simple buffer implementation to collect JIT output - Add support for labels, and link step -...
Proxy syscalls are currently defined in `src/abi/riscv-unknown-abi.h` to match the `riscv-unknown-elf` toolchain. The target syscall set is the minimum set required to run apache with mod_ssl / openssl.
Add generator to generate encode and decode template specialisations using BMI2 PEXT/PDEP - use riscv-host to check for Intel BMI2 support - add mechanism to select optimized decoder template The...
Add a LaTeX instruction table generator that uses some of the additional metadata - use C-based pseudo code from meta/opcode-pseudocode-c - use math based pseudo code from meta/opcode-pseudocode-alt - translate...
Add a generator that uses meta data that maps C operators to functions so that the existing pseudo code used for interpreter generated can be machine translated into Berkeley SoftFloat...
The current bitfield structs in `emu/riscv-machine.h` and `emu/riscv-pte.h` require endian macros in a similar fashion to the register structs in `emu/riscv-processor.h` due to structure bitfield order differences for different emulator...
## Title: Compilation Failure on `sudo make` Due to Missing `` Include in Specific Files ## Description: When attempting to compile the project using `make` with sudo, I encountered multiple...
