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                                            Massimo Gaggero

Wishbone bus high latency in read on Vexriscv CPU "minimal" variant and read/write on others CPU.

Absolutely, according to my understanding, the code is executed directly from the Quad SPI flash. There is no copying of program data to the SRAM. It's important to highlight that...

Keyrock OIDC + oauth2-proxy seems to authorize any enabled user even if not authorized for the application.

At first glance the debug's log shows that no queries are performed to asses whether an user is authorized in the application but only if the user has already authorized...