Markus Faerevaag

## Description During some shift instructions, the shift offset operand is not decoded properly. The lowest five bits should be taken and not the whole operand. Currently the bit base...

## Description The instructions `movaps` and `movdqa` does not enforce the required 16-byte alignment. According to the Intel manual, "When the source or destination operand is a memory operand, the...

## Description When moving segment register (two bytes), for instance `ES`, to register (four bytes), it is invalidly padded. According to the Intel manual, "When executing `MOV Reg, Sreg`, the...

## Description When execution `pop esp` the memory is accessed before incrementing the stack pointer. According to the Intel manual, "The `POP ESP` instruction increments the stack pointer (ESP) before...

## Description When pushing segment registers, as `SS`, `CS`, `DS`, `ES`, `FS` and `GS`, the stack pointer is incremented by four bytes, although the segment registers are only two bytes...

## Description Missing enforcement of memory alignment of `pshufb` with certain values of source operand. Operand should be 16-byte boundary aligned when 128-bit memory. **Reference:** Ref. Intel 64 and IA-32...

## Description Missing signed extension of immediate value when pushing `-0x1`. **Reference:** Ref. Intel 64 and IA-32 Architecture Software Developer's Manual Vol. 2B 4-509 **Affected instructions:** ``` 0x6aff ``` NOTE:...

## Description Missing signed extension of immediate value when pushing `-0x1`. **Reference:** Ref. Intel 64 and IA-32 Architecture Software Developer's Manual Vol. 2B 4-509 **Affected instructions:** ``` 0x6aff ``` NOTE:...

## Description Instruction `xadd` occasionally confuses source and destination operand, by writing to the wrong one. The sum of the operands should be written to the destination operand, i.e. the...

Hi there! I am experiencing issues when trying to sync calendar entries which contain colons. The entry below, for instance, was synced from my caldav server. As you can see,...