A32: CPSR read/write behaviour with MSR/MRS

[merryhime]

Will need to verify this behaviour.

The relevant CPSR execution state bits affected are:

• IT
• J
• T
• E

The v7 manual specifies that CPSR should be read with execution state bits other than E masked out, and that writes do not affect the execution state bits other than E.

i.e. mask value is 0b11111000'11111111'00000011'11011111.

Behaviour differs with ERET and LDM (exception return).

Clearly this behaviour differs from some pre-v6 architectures.