ARM64 Backend

[merryhime]

Framework of ARM64 backend. Aim is for a working A32 support to be done first.

This also involves a redesign of how backends are done, to potentially support multiple threads sharing emulated address spaces, which I plan to backport to the x64 backend.

Very incomplete.

[merryhime]

~~Reminder: Handle fpcr_controlled in FPVector.~~ Done.

[merryhime]

Things to do:

• [ ] Properly implement terminals
• [ ] Properly implement ranged cache invalidation
• [ ] Check ticks in dispatch loop, and other tick related things (consider promoting to persistent register)
• [ ] Check halt in dispatch loop, and other halt related things
• [ ] Fastmem
• [ ] Consider how to make A32AddressSpace multi-thread safe from an invalidation and code emission standpoint
• [ ] Consider turning A32Core into (A32Cpu, core_index) or similar instead, and sharing state in that fashion, with the assumption that library user binds a unique core_index per emulated core, up to a maximum of core_count.
• [ ] Punt A32 specifics (e.g. EmitA32ConditionFailedTerminal and EmitA32Terminal) into EmitConfig callbacks.
• [ ] // TODO: Detect if Gpr vs Fpr is more appropriate
• [ ] Inline A32SetCpsr
• [ ] // TODO: Track latent values
• [ ] Remove unused IR instructions (notably several VectorMultiply variants, and some unused size variants)
• [ ] Consider best way to handle fpcr management around callbacks
• [ ] Consider improving !fpcr_controlled codegen (i.e. tracking fcpr use)
• [ ] RegAlloc: Eliminate move in case of IsLastUse with ReadWrite
• [ ] Implement check_halt_on_memory_access