FIFO reset may get deasserted too late

[marqs85]

Dual-clock FIFO used in the project (generic_fifo_dc_gray.v) is dynamically reset by a common signal of which deassertion is synchronized to both read and write clock domains. In some cases (depending on clock frequencies etc.) sd_data_master asserts FIFO write enable (we) while write pointer (wp_bin) is still under reset. This causes first word of a RX/TX block transfer getting overwritten in the FIFO as the write pointer doesn't get incremented.

Below is a timing diagram captured from an occurence of the issue in generic_fifo_dc_gray1 on FPGA implementation. A block transfer from wb_clk domain writes first word (0x00010203) into FIFO while reset deassertion triggered by en_tx_i assertion launched from sd_clk domain is still being synchonized. The synchronized reset (wr_rst) gets sampled after the write, thus wp_bin stays at zero and second FIFO write overwrites the first word and the whole block transfer gets offset by one word.

I've worked around the issue by removal of the synchronization circuitry which is not ideal solution but should be relatively safe assuming rst is deasserted sufficiently before write enable (we) assertion gets sampled by wr_clk.