Ian McIntyre

> I'm notably **not** bringing up the Ethernet PLL, so next step might be to rule out clock quality issues. I linked with SDK code to simplify PLL1 bringup, remuxed...

A single setpoint also works for PLL1 bring-up, with no analog IP interface needed. The MAC and PHY are up to 100Mbit/s.

> I found the existing driver very hard to use because it requires me to understand the peripheral, which I as a user don't want to have to understand. We...

It's a correct claim. Signaling a driver-specific busy error through the blocking interface is an oversight. I see this affects LPSPI ([example](https://github.com/imxrt-rs/imxrt-hal/blob/29df2d21ad03130d859c29dd97e87cf26c9a8abb/src/common/lpspi.rs#L691-L692)) and LPI2C ([example](https://github.com/imxrt-rs/imxrt-hal/blob/29df2d21ad03130d859c29dd97e87cf26c9a8abb/src/common/lpi2c.rs#L664)); let me know if you've...

Clearing the FIFO, particularly the RX FIFO, is important for error recovery. Suppose we're using the LPSPI to transfer (send and receive) data. While we're filling up the TX FIFO...

I'm sorry for the trouble. Could you share some pseudocode or a call sequence that demonstrates what you were debugging? I'd like to learn more about what went wrong. I...

Thanks for sharing. I see that, no matter the busy indication, we don't need to clear the FIFOs. #157 is my attempt at fixing the busy error for the LPSPI...

Tips, pointers, suggestions: - Chapter 48 in the 1060 reference manual (RM) covers the the LPSPI peripheral. The peripheral is the same across all supported MCUs. - The PCS for...

Good thoughts. I'm happy to help with you / others with that deeper look. > Having the chip select as part of the driver initialization (LPSPI::new()) seems a bit strange....

If you're curious about how RTIC manages resources, it's documented [here](https://rtic.rs/1/book/en/by-example/resources.html). RTIC uses granular critical sections to ensure mutual exclusion of a resource. Here's some pseudo-code to show how a...