mbitsnbites

The instruction should transfer a single element from a vector register to a scalar register. Note that this instruction goes against the regular model of scalar and vector operations since...

Add a "get mask" instruction for vector registers

1

Add an instruction that queries the "mask state" of vector registers. The instruction should take one or two vector registers as source operands and a scalar register as the destination...

User administration interface.

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I have not found a good interface for administering users. Users can add themselves easily, but as a Critic admin it would be nice to be able to remove /...

"Failed to validate commented lines" after rebase

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After rebasing (new upstream), any attempt to add an issue to a commit (older than the rebase in this case) will result in a dialog saying "Failed to validate commented...

This is usually not a problem, but in some degenerate cases (still to be investigated) lots of direct mode cache entries may be added, without any preprocessor mode cache entries...

## Problem We already have `SEQ`, and we can branch on `BNS`, for instance. Thus `SNE` appears to be superfluous (eating up encoding space). Investigate if any code sequences would...

Here is a draft of my ideas that I came up with yesterday. ## Caveat emptor Take it for what it is: A sketchbook proof of concept experiment, totally untested....

With late forwarding of the addend, the MADD instruction would work as an MAC with zero latency for consecutive multiply+add operations such as: ``` madd r1, r2, r3 madd r1,...

It should be relatively easy to "pop bubbles" during a stall (i.e. don't propagate the stall signal to earlier stages if a stage is currently holding a bubble).

The ICache is more important than the DCache for most applications, and it is easier to implement. Having an ICache will leave the shared memory bus free for the data...