Matt Venn

http://mattvenn.net

@YosysHQ-GmbH @TinyTapeout Valencia, Spain Engineer and Science Communication. On a mission to make ASICs more accessible. YosysHQ & Tiny Tapeout founder member.

Results 102 comments of


                                            Matt Venn

add an override for the active pin

shift register with clock, data & reset on external pins logic analyser can override output active enable limited to 1 at once

fix module tests

tomorrow*

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