mattfel1

There are some erroneous DRAM signals that cause vivado to crash. They are coming from somewhere that I haven't traced down yet but is probably related to my CXP backend...

Accum Analyzer Messing Up Cases

1

Accum Analyzer seems to be missing cases to optimize an accumulation and is doing the optimization in cases where it shouldn't. See https://github.com/stanford-ppl/spatial/blob/develop/test/spatial/tests/compiler/AccumReplacements.scala for a variety of cases we expect...

Banking to Struct Optimization

1

In cases where it makes sense to turn N banks into a struct with N elements and store them all at the same address of an SRAM

For example: `sram2 load dram2(0::64 par P, 0::64)` This compiles in spatial successfully, but crashes chisel compilation because it's confused about how the unroller created two streams that both share...

Unset value (for --sim)

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X is the default, unset value. It may be nice to be able to set something to this as well.

Pipe Insertion + Streaming Controller

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The original problem is that if you do something like ``` Stream.Foreach(N by 1){i => val ctrmax = sram(i) Foreach(ctrmax by 1){j => ... } } ``` The original pipe...

Use protobuf serialization between chisel3 and firrtl

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Some big apps get random firrtl errors, so it seems the best way to bypass this is to use protobuf inbetween chisel and firrtl to avoid the firrtl parser. This...

Warning for Const out of range Missing

2

We had this case: `local_edges_l(container_begin + edge_iter) & 0x8000000000000000l` where local_edges_l is `FixPt[TRUE,_64,_0]`. It didn't warn about 0x8000000000000000 being out of range, but the generated verilog had 0x7fffffffffffff secretly, which...

I have a few unit tests that I thought should expose this, but apparently they don't. I noticed in SHA1 that `sha_data(i) = cat(buffer(base + i*4+3).as[U8].asBits, buffer(base + i*4+2).as[U8].asBits, buffer(base...