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alivu13p的part型号的speed/temp grade好像应该是-2L-e,而不是-2-i.

Open xiongyw opened this issue 2 years ago • 4 comments

根据芯片上二维码扫描的结果(https://support.xilinx.com/s/question/0D54U00007H2baYSAR/), 应该是-2L-e.

另外,根据DS890 figure 4那一页的说明, L2或-2L中的 L 指的是 Vccint 可以取两种,0.72v 或 0.85v, 区别在功耗和性能的取舍。-2的型号就是0.85v,没有0.72v核心电压的选项。如果-2L选用0.85v,应该和-2没有差别。阿里vu13p的卡从SysMon里看到Vccint是0.85v,所以这个片子,在vivado里面选,应该是-2L-e和-2-e都行。另外,vivado里面part还有一个选项, -2LV-e,好像如果阿里的卡核心供电是0.72v的话,就应该选这个。

总结一下,从使用角度说,alivu13p的part在vivado里面应该选 -2L-e 或 -2-e 都行,两者在vivado里面part的相关参数一模一样。选 -2L-e 好像更严谨一些。

xiongyw avatar Aug 27 '23 05:08 xiongyw

There is also a trade-off in the PCIe core. At 0.72v, the PCIE4 core clock is limited to 250 MHz, so it cannot run at gen 3 x16.

alexforencich avatar Aug 28 '23 18:08 alexforencich

There is also a trade-off in the PCIe core. At 0.72v, the PCIE4 core clock is limited to 250 MHz, so it cannot run at gen 3 x16.

That's awesome, turns out it's the real alexforencich!

Welcome to the vu13p project. vu13p is an FPGA hash accelerator developed by a certain company. This accelerator has been phased out by major server vendors, and someone with good intentions reverse-engineered its pin constraint file. This repository serves as a collection of related materials.

In the example repository, we've referenced your IIC master/slave repository and developed a driver for it on an x86 host. Your design of the CMD for the IIC master has significantly streamlined the process of writing an IIC driver. experiencing it during software programming feels incredibly smooth! It's trulyyyyyyyy fantastic.

maswx avatar Aug 29 '23 03:08 maswx

根据芯片上二维码扫描的结果(https://support.xilinx.com/s/question/0D54U00007H2baYSAR/), 应该是-2L-e.

另外,根据DS890 figure 4那一页的说明, L2或-2L中的 L 指的是 Vccint 可以取两种,0.72v 或 0.85v, 区别在功耗和性能的取舍。-2的型号就是0.85v,没有0.72v核心电压的选项。如果-2L选用0.85v,应该和-2没有差别。阿里vu13p的卡从SysMon里看到Vccint是0.85v,所以这个片子,在vivado里面选,应该是-2L-e和-2-e都行。另外,vivado里面part还有一个选项, -2LV-e,好像如果阿里的卡核心供电是0.72v的话,就应该选这个。

总结一下,从使用角度说,alivu13p的part在vivado里面应该选 -2L-e 或 -2-e 都行,两者在vivado里面part的相关参数一模一样。选 -2L-e 好像更严谨一些。

cool ! 马上改掉!

maswx avatar Aug 29 '23 03:08 maswx

There is also a trade-off in the PCIe core. At 0.72v, the PCIE4 core clock is limited to 250 MHz, so it cannot run at gen 3 x16.

厉害了,Alex 还认识中文?!!Hello Alex, I learnt a lot from your youtube channel, thanks :)

xiongyw avatar Nov 03 '23 04:11 xiongyw