Marlon James
Marlon James
It depends on when in the time step the VPI application attempts to register it. More precisely, if you attempt to register for a `cbAtStartOfSimTime` callback with a time that...
A `packages` attribute could be added to `simulator` as a list of handles to the package instantiations. For VHPI, here's an example snippet from the language ref manual showing how...
One more vote for a method on `simulator`. There is already `simulator.get_root_handle`, so probably `simulator.get_packages`. I think it makes sense to have each package be a `HierarchyObject`, and we should...
@ktbarrett Yeah it looks like they only support **IEEE 1364-2005** VPI (partially) at the moment.
GHDL has `Get_Package_Inst`: https://github.com/ghdl/ghdl/blob/657fcfde5fb93c1311fe5fd2d28146c89852614d/src/grt/grt-avhpi.ads#L427 It might not be too much work to support `vpiPackage` only.
It has not, and I'm not aware of anyone currently working on it.
Active-HDL allows compiling Verilog/SystemVerilog modules in any order. You do get a compilation warning: `Warning: VCP2515 /cocotb/examples/mixed_language/hdl/toplevel.sv : (100, 3): Undefined module: endian_swapper_vhdl was used. Port connection rules will not...
This test should have caught the issue if simulators followed the LRM: http://github.com/cocotb/cocotb/blob/2d597279f6dd2e98136854d7cebdd8a1293955ca/tests/test_cases/test_cocotb/test_timing_triggers.py#L148-L157
I know we usually prefer not to have simulator-specific workarounds, but this seems like a good candidate for it.
IEEE 1800-2012 Clause 39 has details on assertion API, including VPI callbacks you can register. 40.5 has details on assertion coverage.