Mark Charney

Intel AMX support has been pushed in the public version of XED. The Intel SDE that supports Intel AMX had/has a binary version of XED that supported AMX (before my...

x87 is a little strange. Technically you are right. This is some of the oldest stuff in XED. I do not recall what MS disasm did at the time. But...

i hear what you are suggesting. I'll think about it. I do not mind changing the *32 function to barf on 64b registers as input. And I don't mind making...

(and sorry about accidental closing of the issue. I was looking to label the issue "acknowledged" using the mobile/phone interface to github and failed miserably.)

I fixed the first part locally. Not sure what I want to do about the 2nd part (largest enclosing reg for R15B in 32b mode). One option would be to...

I started to work on this one. I have fixed the 1st and 4th issues in my work area. Thanks. I believe the SDM may be wrong for the 5th...

I try not to bash the SDM. The current owner is a friend of mine and was handed a document with a lot of technical debt. We are constantly working...

Fixed the 2nd one too. That was probably 16y old bug.

I fixed all but the last one now. Thinking about whether it is worth bothering. Those are the only 2 instr with "~4b" imm when there is a register in...

FWIW, I got a response back from the decoder team. As I suggested above, Table 2-39 is wrong for EVEX.V'. For EVEX.V' (P[19]), the table should say "if 0" in...