RISC-V-TLM
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mariusmm
AT model
You provide an LT model, is an AT model for more detailed performance analysis also on your roadmap?
Hello Matthias,
thank you for your interes on this project.
Currently I'm evaluating what I should add to the simulator and write some roadmap. Do you think is interesting to add the AT model? May be it's a matter to change only the MemoryInterface.cpp with a more complex interface (AT model) and thats all? It would also require a AT model for memory, do you have one we can use?
Thank you!
Màrius
Yeah this is actually the reason why I'm asking: we have a AT DRAM model, because for precise modelling of DRAM you need AT. An LT DRAM model makes no sense at all.
Here is the link to our DRAM and DRAM controller model DRAMSys: https://github.com/tukl-msd/DRAMSys
I think I can add a AT model just writing a new MemoryInterface module using AT. The easiest way would be that each function (writeDataMem / readDataMem) perform one single entire transaction before return (no transaction pipelinin). Do you think this implementation can be useful for you?
You can take a look at https://github.com/mariusmm/RISC-V-TLM/blob/AT/src/MemoryInterfaceAT.cpp where there is a basic and dirty implementation. What do you think?
I think this would not make much of a difference to LT, because a real core would do transaction pipelining. I think this behaviour is more less the same as the blocking transport. The core could not exploit the memory system efficiently.
However, if we model maybe many in-order cores then this could make already some sense 👍