Some questions about hardware constraint

[white-jing]

Hello, thanks for open-sourcing great tool!

I am comparing hardware simulation against the tool, but I see big discrepancies with the result. I suspect the tool has made some assumptions, so I want to ask some questions about hardware constraints and the code and get confirmed.

1. In the maestro doc, it says it supports any level of hierarchies. https://maestro.ece.gatech.edu/docs/build/html/hw_supported.html. When level is 2, does it assume noc_bw for noc level 1 and noc level 2 are same?
2. There are lots of places in the code where it assumes the level is 2 at maximum. (e.g. loop iteration assumes level-2). Do you have any tutorials to run archietecture with more than 2 levels of hierarchy?
3. multicast parameter doesn't seem to be used anywhere. Does it assume multicast from L2 memory to L1 is always available?
4. Does it assume that the word size of partial sum is same as input/filter data?

Thanks again