Torsten Maehne

I am not able to reproduce the issue on my side. It may be related to some issue outside our influence, e.g. some interaction of a particular JDK version with...

@DevBlocky: We have not yet discussed a target date for a new stable release. From our side, a release before the start of the spring term would make sense. @BFH-ktt1:...

Your feature request is sensible. Due to our limited resources, it is not of high priority for us. PRs in this direction are welcome!

This may be related to PR #1798 by @BFH-ktt1. Support for the alchitry au io board was added by @chuckb in PR #1648. We don't use neither Vivado nor the...

@berryboy2012: We need the requested information to work on this issue without additional effort.

I agree with you analysis and suggested manual fix to the netlist. PRs to fix this issue are welcome! @BFH-ktt1: Could you maybe have a look what goes wrong?

Thanks for reporting this issue! I can confirm that invalid VHDL code gets generated for this schematic:  The VHDL architecture of circuit `main` looks like this: ```vhdl ARCHITECTURE platformIndependent...

To facilitate testing of your improvements, could you please provide a `.circ` file (as ZIP archive attached to a message) as well as screenshots showcasing the newly introduced capabilities by...

Before investing a lot of effort in development, it may make sense to first discuss the requirements and how you intend to implement them in the GUI of Logisim-evolution.

> One thing I would like to discuss is if the probe dynamic shape should be a rounded rectangle (alike the component) or just the text (which would be more...