Torsten Maehne

Please provide reproducers for your above issues in form of one or several (zipped) `.circ` files. Ideally, please also show relevant snippets of the wrongly generated VHDL code. It will...

Thanks for the reproducer. Which Logisim-evolution are you actually using? On which platform? Which logic synthesis tool? Have you tried with the [nightly builds](https://github.com/logisim-evolution/logisim-evolution/#nightly-builds)?

> [...] > > 2. IEEE Std 1076-2008 section 6.5.7 says: > > > ... every scalar subelement of the explicitly declared interface object shall be associated exactly once with...

> I've already created a separate issue regarding the flip-flops. You mean issue #1874. > I also noticed, my patch regarding the partial maps to open caused other issues resulting...

Thanks for the report and sorry for the late reaction from our side. I can reproduce the issue with your example. It might be relatve to issue #1452. We lack...

I can confirm the issue, as it was observed by our students in the past during their Logisim projects, in which they collaborated in small groups and tried to better...

Using libraries remains fragile, despite it is working now in your case. It's up to you to decide whether you want to close this issue. > It’s too bad someone...

Yes, this would be a useful enhancement. However, auto-saving should not happen to the opened circuit file, but rather a separate file, which gets automatically loaded by Logisim-evolution when it...

Current workaround if this issue affects the usability due to the circuit size is to disable "Simulate -> Auto-Propagate" during the design of the circuits and only enable it when...

@BFH-ktt1 is familiar with this aspect of the code base and should be able to confirm whether your approach is right. Your enhancement proposal sounds anyway useful to me.