Optimization: collapse common sets of instructions to one instruction.

[machinamentum]

Some sets of instructions are very commonly generated by MIPS compilers. These can be optimized to be executed as a single instruction together instead of suffering from the overhead of executing two or more emulated instructions.

Example

lui t0, 0x1FB0
ori t0, t0, 0xF560

These instructions together effectively move a 32-bit immediate into register t0 and can be optimized into a single "move 32-bit immediate" instruction. Since this requires already decoding sets of instructions together, the interpreter requires a mechanism to pool together pre-decoded instructions that can later be executed without re-decoding, speeding up small loops. This also would enable a quick way to discard nops (commonly implemented as sll zero, zero, 0 in most compilers).