migen.fhdl.specials: add per bit oe option to TSTriple

[TomKeddie]

[sbourdeauducq]

Has this been tested? The Verilog output is something like:

assign i2c_sda = satellite_i2c_tstriple1_oe ? satellite_i2c_tstriple1_o : 1'bz;

Does that do the right thing when oe is more than 1 bit?

[TomKeddie]

I created a set of tests at https://github.com/TomKeddie/prj-litex/tree/master/icebreaker/perbitoe. I couldn't trip the TRELLIS_IO case easily but everything else is as expected.

tom@z400:~/git/TomKeddie/prj-litex/icebreaker/perbitoe$ make
diff origin/arty_a7_build/top.v     branch/arty_a7_build/
diff origin/icebreaker_build/top.v  branch/icebreaker_build/
diff origin/papilio_pro_build/top.v branch/papilio_pro_build/
diff origin/versaecp55g_build/top.v branch/versaecp55g_build/
diff origin/arty_a7_build/top.v     perbitoe/arty_a7_build/
9c9
< wire module_oe;
---
> wire [1:0] module_oe;
make: [Makefile:24: diff_origin_perbitoe] Error 1 (ignored)
diff origin/icebreaker_build/top.v  perbitoe/icebreaker_build/
9c9
< wire module_oe;
---
> wire [1:0] module_oe;
46c46
< 	.OUTPUT_ENABLE(module_oe),
---
> 	.OUTPUT_ENABLE(module_oe[0]),
55c55
< 	.OUTPUT_ENABLE(module_oe),
---
> 	.OUTPUT_ENABLE(module_oe[1]),
make: [Makefile:25: diff_origin_perbitoe] Error 1 (ignored)
diff origin/papilio_pro_build/top.v perbitoe/papilio_pro_build/
9c9
< wire module_oe;
---
> wire [1:0] module_oe;
make: [Makefile:26: diff_origin_perbitoe] Error 1 (ignored)
diff origin/versaecp55g_build/top.v perbitoe/versaecp55g_build/
9c9
< wire module_oe;
---
> wire [1:0] module_oe;
make: [Makefile:27: diff_origin_perbitoe] Error 1 (ignored)