migen
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A Python toolbox for building complex digital hardware
This fixes exceptions when running the litedram tests. See below for the log of one of the test failures this fixes. The other test failures are pretty much identical. ```...
Adding a new Module method that prints the hierarchy. Useful for visualising the structure of a module. I'm adding this PR mainly to start a conversation about where is best...
I have the following in a Migen module: ```py self.comb += [ # Always valid self.tx.tvalid_i.eq(1), # Throw away receiver data self.rx.tready_i.eq(1), # Clear an error if one occurs self.rx.error_clear_i.eq(self.rx.error_o),...
For FMC TDC and Shuttler debugging, I've created some helpers for dealing with FMC that I'd like to submit to your critical review ;-). ### Observations * FMC standard offers...
Hello, When I trying to simulate the FSM behavior then I found the below issue: In my code: ``` fsm.act("STATE_1", If(self.trigger_2, NextState("STATE_2"), ) ) # Delay 4 clock circles when...
The `ecpbram` utility expects the ROM data file to be in a fixed width (i.e. zero-padded) format. migen should be able to adhere more strictly to that format without breaking...
I work with a xilinx FPGA (spartan 6), with the ise toolchain, when i try to run the lab002 from fpga_101 i have an xst problem: ERROR: Xst: 2927 -...
I would like to split the build process of a design on two hosts: - the first host would call `platform.build(run=False)` and create a build folder with the files required...
Consider this minimal example: ```python from migen import * from migen.fhdl import verilog class my_module(Module): def __init__(self): self.input = Signal(8) self.output = Signal(32) self.comb += self.output.eq(Cat(self.input, self.input+1, self.input+2, self.input+3)) def...
Hi, The code generated of FSM does not capture the `FSM()` object name (similar to `Signal()`), due to this the traces in VCD file has signal names like fsm0, fsm1...
