artiq
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m-labs
A leading-edge control system for quantum information experiments
# Bug Report ## One-Line Summary Phaser can enter "lock up" state that requires a power-cycle due to an interrupted experiment ### Steps to Reproduce 1. Run an experiment that...
The comm kernel roundtrip to allocate extra memory for an RPC result has extremely high latency, to the point where it is easy to make the master-to-core-device TCP connection time...
The ARTIQ compiler embeds host Python values into the compiled program (e.g. for class attributes accessed from kernels) by synthesizing an AST fragment that reproduces the value, and then using...
In https://github.com/m-labs/artiq/issues/795#issuecomment-605371138 @sbourdeauducq said > Sometimes (and rarely AFAICT) the DRTIO link appear to become corrupted with some bitstream builds (visible symptom is a storm of broken aux packets); making...
# Bug Report ## One-Line Summary When using a RAM profile to run a frequency sweep on a AD9910, the output power of the DDS channel is dependent on the...
# Bug Report ## One-Line Summary Unable to measure a consistent slack for preventing DMA RTIO Underflow with KC705. ## Issue Details The measured value seems dependent on whether `print`...
# Bug Report ## One-Line Summary When switching on an Urukul channel TTL with `cfg_sw()`, the other Urukul channels on the same board are set to a value corresponding to...
Do parts of the ARTIQ codebase override or clear default Python types? For the most part I have been able to get around these issues, but now it has become...
## One-Line Summary The startup kernel should not be interruptable by other kernels. ## Issue Details ### Steps to Reproduce 1. Flash core device with a startup kernel that takes...