ad9910: fix the type of ram data

[ntantio]

the type of ram data remains int32 on core device, but changes to int64 on host PC after bitwise operation

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	Type
✓	:bug: Bug fix

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[ntantio]

On host PC, self.amplitude_to_asf(amplitude[i]) << 18 will change the data type from int32 to int64, which will result in the following error.

root:While compiling <repository>/dds_amp_ramp.py
<repository>/dds_amp_ramp.py:43:28-43:40: error: cannot unify list(elt=numpy.int64) with list(elt=numpy.int32): 64 is incompatible with 32
        self.dds.write_ram(self.amp_ram)
                           ^^^^^^^^^^^^
<repository>/dds_amp_ramp.py:43:28-43:40: note: expression of type list(elt=numpy.int64)
        self.dds.write_ram(self.amp_ram)
                           ^^^^^^^^^^^^

Test code is below.

from artiq.experiment import *
from artiq.coredevice import ad9910


class DdsAmpRamp(EnvExperiment):
    kernel_invariants = {"amp_ram"}

    def build(self):
        self.setattr_device("core")
        self.cpld = self.get_device("urukul0_cpld")
        self.dds = self.get_device("urukul0_ch0")

    def prepare(self):
        self.num = 2**7
        time_step = 20 * us
        self.time_step_ram = int(time_step * 1e9 / 4)

        amp = [0.0] * self.num
        self.amp_ram = [0] * self.num
        for i in range(self.num):
            amp[i] = (i + 1) / self.num
        self.dds.amplitude_to_ram(amp, self.amp_ram)

    @kernel
    def run(self):
        self.core.reset()
        self.cpld.init()
        self.dds.init()

        self.core.break_realtime()
        self.dds.set_cfr1(ram_enable=0)
        self.cpld.io_update.pulse_mu(8)

        self.dds.set_profile_ram(
            start=0,
            end=self.num - 1,
            step=self.time_step_ram,
            profile=0,
            mode=ad9910.RAM_MODE_CONT_RAMPUP,
        )
        self.cpld.set_profile(0)
        self.cpld.io_update.pulse_mu(8)
        self.dds.write_ram(self.amp_ram)

        self.dds.set_cfr1(
            ram_destination=ad9910.RAM_DEST_ASF, ram_enable=1, osk_enable=0
        )

        self.dds.set_frequency(1 * MHz)
        self.dds.set_att(0.0 * dB)

        self.cpld.io_update.pulse_mu(8)
        self.dds.sw.on()

[ntantio]

The methods turns_to_ram() and turns_amplitude_to_ram may also need to change, but I have not used them before.