svd2zig

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Changes to support missing comments and missing access fields

4

osterwood

destination type 'u32' has size 4 but source type has size 5

5

When trying to write to a register, I'm getting a size mismatch. ```zig HW.tim3.cr1.write(.{ .cen = .enabled }); ``` gives the error: ``` ./src/hw/stm32f0x0.zig:29:39: error: destination type 'u32' has size...

lynaghk

simonschmidt

Expose bit-banded register access

1

Some arm processors expose [bit-banding](https://developer.arm.com/documentation/ddi0337/h/programmers-model/bit-banding) to read/write bits of peripheral registers. This provides more efficient access when reading/writing a single bit in a register It would be convenient to expose...

simonschmidt

Handle cases where `` is declared inside `` rather than as a direct child of `` For example the stm32f103 SVD has registers like this: https://www.st.com/resource/en/svd/stm32f1_svd.zip ``` ... RCC CR...

simonschmidt