Luke Gorrie

> 10G PHY (Marvell 88X3310) - XAUI - ECP5 - XGMII - ECP5-5G - PCIe x4 Awesome! So the idea is that one ECP5 talks high-speed SERDES to the 10G...

> Yes, but it's better not to reinvent the wheel =) Right. I only mean that if we are looking for an existing open-source core then we might find something...

> But this PHY provides min. 2 ports 10G. If we were "stuck" with a second SFP+ then we could connect that up to the FPGA for future use. Myricom...

Ouch! @daveshah1 is it really true that PCIe ECP5 dev boards are not available anymore??

@insekt And from your past research one potential alternative is a Kintex7 board with PCIe x8 and 4xSFP+ from Aliexpress for $166? https://www.aliexpress.com/item/xilinx-board-xilinx-fpga-board-xilixn-fpga-development-board-pcie-board-Kintex-7-XC7K420T-XC7K325T-xilinx/32907109444.html

@insekt What do you think about using an ECP5 board with PCIe x1 for prototyping and derisking? Could this be sufficient for everything except the full-speed PCIe core? (Guessing we...

Tonight a few of us will gather at [JAM Hotel](https://goo.gl/maps/p9V6WU8Rsc92) for beer and pizza starting around 8pm. Maybe meet up with people somewhere later. We can also use the Snabb/RaptorJIT...

This idea sounds highly plausible to me! Thanks for sharing it. I can imaging that some code will JIT poorly today and would be helped by this change. Maybe it...

Is the problem that the modulus is not a constant?

(There are two related missing optimizations right? One is to convert divisions by powers of two into bitshifts and the other is to inline divisions into the trace for constant-but-not-power-of-two?)