[syn] Check with tool vendors how out of range enum assignments / casts are synthesized

[msfschaffner]

Spun out from #9391. We want to check how synthesis tools treat casts from a logic vector to an enum variable of the same size, e.g.:

  parameter int MuBi4Width = 4;
  typedef enum logic [MuBi4Width-1:0] {
    MuBi4True = 4'hA, // enabled
    MuBi4False = 4'h5  // disabled
  } mubi4_t;

logic [MuBi4Width-1:0] inputval;
mubi4_t enumvar;

assign enumvar = mubi4_t'(inputval);

In particular, we are interested in how this cast behaves if inputval is not within the defined enum range (i.e., not MuBi4True nor MuBi4False in this example).

We basically want to make sure that the casts do not get synthesized into a "filter" that collapses invalid encodings into one value.

[msfschaffner]

We probably want to check with Synopsys, Cadence and Xilinx at the moment.

[tjaychen]

@arnonsha @Jacob-Levy

Arnon / Jacob / Michael, If we haven't filed a solvenet ticket already, is this something Nuvoton can take on to confirm and let us konw? I think as @msfschaffner synopsys is probably the highest priority at the moment.

[msfschaffner]

Indeed, Synopsys would be the highest priority. I have not filed the ticket just yet.

[arnonsha]

Michael I think before going to snps with this, can you check what was imlemented in the netlist ? If I understamd correctly the logic is wrapped in a hierarchy which can be isolated from netlist and even simulated with legit and non kegit values.

[vogelpi]

This seems worth and investigation with Synopsys DC. I'll bring this up in the relevant meeting.

[andreaskurth]

@vogelpi to talk to the PD team, together with him reaching out about AES. PD team may not be available before Tuesday, though.

[vogelpi]

I've reached out to @meisnere about this now.

[andreaskurth]

PD team is working on this. Discussed in triage meeting and agreed to continue tracking this in M4

[moidx]

We don't have any SiVal results indicating that this was an issue for Z1. For Earlgrey-PROD.M4 we have ran out of time to be able to make any RTL changes.

This should be tagged as future release, but marking as M5 to follow up with @meisnere.

[meisnere]

Synthesized the following module:

module test #(parameter int MuBi4Width = 4) (
  output logic [MuBi4Width-1:0] outval
);

  typedef enum logic [MuBi4Width-1:0] {
    MuBi4True = 4'hA, // enabled
    MuBi4False = 4'h5  // disabled
  } mubi4_t;

logic [MuBi4Width-1:0] inputval;
mubi4_t enumvar;

assign inputval = 4'h6;
assign enumvar = mubi4_t'(inputval);

assign outval = enumvar;

endmodule

outval got the value of 4'h6, so the casting didn't change inputval value to 4'h5 or 4'hA.

Did the same test with inputval=4'hA, outval got the value of 4'hA as expected.

[vogelpi]

Thanks @meisnere for doing the experiment and feeding the information back! It sounds like we are on the safe side and it's good to know that :-)

We should do a similar experiment with Xilinx and Cadence tools but this isn't a priority for Earlgrey-PROD obviously. I am thus moving the issue to Backlog for now.