[dv] Predict value after a read of an RC field in shadow_reg_errors

[rswarbrick]

The sequence runs without the scoreboard enabled, so the sequence is responsible for updating the RAL. This commit adds a missing update.

The motivation for this was to fix the shadow_reg_errors test for ac_range_check (thanks, @martin-velay, for discovering the problem). Try that out with util/dvsim/dvsim.py hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson -i ac_range_check_shadow_reg_errors -t xcelium --fi=1.

[rswarbrick]

(Annoyingly, the test still fails after this change, but it gets much further and it's exploding on something unrelated, so I thought this was worth doing as a first step!)

[martin-velay]

Thanks a lot Rupert for working on this. I wonder why it has never been raised before. Do you have any clue?

[martin-velay]

@rswarbrick, I have "cherry-picked" your modification on the master and your commit fixes the issue I raised. It works well for tests ac_range_check_shadow_reg_errors and ac_range_check_shadow_reg_errors_with_csr_rw.

Command: util/dvsim/dvsim.py hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson -i ac_range_check_shadow_reg_errors ac_range_check_shadow_reg_errors_with_csr_rw

Thank you very much!

[rswarbrick]

Oops: it looks like I forgot about this PR (sorry). I've just rebased and force-pushed, and will merge if everything looks good in an hour or two.