[chip-test, aes] chip_sw_aes_masking_off

[johngt]

Test point name

chip_sw_aes_masking_off

Host side component

Rust?

Opentitantool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

• [ ] None
• [ ] CW310
• [ ] Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [ ] Device-side (C) component developed
• [ ] Bazel build rules developed
• [ ] Host-side component developed
• [ ] Test added to dvsim nightly regression (and passing at time of checking)
• [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

[vogelpi]

This is a duplicate of #19985. The test is implemented already but to to test that it works a full SCA evaluation setup is needed. We're doing this as part of the penetration testing but using a different test routine.

This particular test here only runs on dvsim. That's why this test doesn't have a si_stage in the test plan. @johngt , would you like me to make on note on this in the testplan? Or is it fine to just close the issue and the information this information is tracked somewhere else?

[johngt]

Given that it will not be tested in SiVal could you please mark si_stage to NA. Thanks @vogelpi

[vogelpi]

Thanks for the quick feedback @johngt , the PR is here: #21638