[chip-test] Incomplete SiVal Stage 1 and 2 tests

[johngt]

Description

The following are a list of tests do not have a corresponding bazel test in the testplan and that are marked as SV1 and SV2. Individual issues will be created but this is just for highlighting specific blocks that have SV1/2 effort outstanding.

adc_ctrl (Nuvoton)

• [ ] chip_sw_adc_ctrl_normal

aes (Google)

• [x] chip_sw_aes_enc https://github.com/lowRISC/opentitan/pull/21284

csrng (Google)

• [x] chip_sw_csrng_edn_cmd https://github.com/lowRISC/opentitan/pull/21285

gpio (zeroRISC)

• [x] chip_sw_gpio_out https://github.com/lowRISC/opentitan/pull/21312
• [x] chip_sw_gpio_in https://github.com/lowRISC/opentitan/pull/21312

hmac (Google)

• [x] chip_sw_hmac_enc https://github.com/lowRISC/opentitan/pull/21285
• [ ] chip_sw_lc_ctrl_kmac_req

keymgr (Google)

• [ ] chip_sw_keymgr_derive_attestation

kmac (Google)

• [x] chip_sw_kmac_enc https://github.com/lowRISC/opentitan/pull/21285

lc_ctrl (Google)

• [ ] chip_sw_lc_ctrl_jtag_access
• [ ] chip_sw_lc_ctrl_volatile_raw_unlock
• [ ] chip_sw_lc_ctrl_debug_access

otp_ctrl (Google)

• [ ] chip_sw_otp_ctrl_keys
• [ ] chip_sw_otp_ctrl_entropy
• [ ] chip_sw_otp_ctrl_program
• [ ] chip_sw_otp_ctrl_hw_cfg0
• [ ] otp_ctrl_calibration

pwrmgr (zeroRISC)

• [ ] chip_sw_pwrmgr_external_full_reset

usbdev (lowRISC)

• [ ] chip_sw_usbdev_mem