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Eth 8packets
Hi, I'm wondering what does the value {3'H7,{7{3'H5}}} indicates? It was found in Line 98
` if ((rx_nxt == {3'H7,{7{3'H5}}}) && (byte_sync == 0) && (sync == 0))`
Based on the codes given, it seems like is checking the end of 8th (collected) RX packets which each packet is 3 bits size. However, I couldnt figure out the how did it comes to value H7 and H5?
In this case the coding is RMII, so it is checking two data bits and receive enable.
Sent from my iPhone
On 24 Dec 2018, at 05:39, clare7 [email protected] wrote:
Hi, I'm wondering what does the value {3'H7,{7{3'H5}}} indicates? It was found in Line 98
if ((rx_nxt == {3'H7,{7{3'H5}}}) && (byte_sync == 0) && (sync == 0))Based on the codes given, it seems like is checking the end of 8th (collected) RX packets which each packet is 3 bits size. However, I couldnt figure out the how did it comes to value H7 and H5?— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub, or mute the thread.
In that case, why does it has to be 7 of ,{3'H5} ? In order to check for the SFD 1101 0101 isnt that 3 of {3'H5} will suffice for coding in RMII?
On Mon, Dec 24, 2018 at 3:52 PM jrrk [email protected] wrote:
In this case the coding is RMII, so it is checking two data bits and receive enable.
Sent from my iPhone
On 24 Dec 2018, at 05:39, clare7 [email protected] wrote:
Hi, I'm wondering what does the value {3'H7,{7{3'H5}}} indicates? It was found in Line 98
if ((rx_nxt == {3'H7,{7{3'H5}}}) && (byte_sync == 0) && (sync == 0))Based on the codes given, it seems like is checking the end of 8th (collected) RX packets which each packet is 3 bits size. However, I couldnt figure out the how did it comes to value H7 and H5?— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub, or mute the thread.
— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/lowRISC/lowrisc-chip/issues/102#issuecomment-449698888, or mute the thread https://github.com/notifications/unsubscribe-auth/AcHzHLYMMmp5XSBN3x3VVofBZyYui36Pks5u8Ie5gaJpZM4ZgJRm .
-- Regards, Ming
You could certainly adapt the code to only check a single byte but thereby the chance of a false sync could be increased. Bearing in mind the chance of a bit error is greater early on in the packet due to the possibility of contention from multiple transmitters.
Sent from my iPhone
On 26 Dec 2018, at 04:56, clare7 [email protected] wrote:
In that case, why does it has to be 7 of ,{3'H5} ? In order to check for the SFD 1101 0101 isnt that 3 of {3'H5} will suffice for coding in RMII?
On Mon, Dec 24, 2018 at 3:52 PM jrrk [email protected] wrote:
In this case the coding is RMII, so it is checking two data bits and receive enable.
Sent from my iPhone
On 24 Dec 2018, at 05:39, clare7 [email protected] wrote:
Hi, I'm wondering what does the value {3'H7,{7{3'H5}}} indicates? It was found in Line 98
if ((rx_nxt == {3'H7,{7{3'H5}}}) && (byte_sync == 0) && (sync == 0))Based on the codes given, it seems like is checking the end of 8th (collected) RX packets which each packet is 3 bits size. However, I couldnt figure out the how did it comes to value H7 and H5?— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub, or mute the thread.
— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/lowRISC/lowrisc-chip/issues/102#issuecomment-449698888, or mute the thread https://github.com/notifications/unsubscribe-auth/AcHzHLYMMmp5XSBN3x3VVofBZyYui36Pks5u8Ie5gaJpZM4ZgJRm .
-- Regards, Ming — You are receiving this because you commented. Reply to this email directly, view it on GitHub, or mute the thread.
Noted. Thank you. I also notice that there is no signal that triggers *tx_axis_tready . *Did I miss out something?
if (tx_axis_tready) begin tx_frame_addr <= tx_frame_addr + 1; tx_axis_tlast <= (tx_frame_addr == tx_packet_length-2) & tx_axis_tvalid_dly; end
On Wed, Dec 26, 2018 at 8:36 PM jrrk [email protected] wrote:
You could certainly adapt the code to only check a single byte but thereby the chance of a false sync could be increased. Bearing in mind the chance of a bit error is greater early on in the packet due to the possibility of contention from multiple transmitters.
Sent from my iPhone
On 26 Dec 2018, at 04:56, clare7 [email protected] wrote:
In that case, why does it has to be 7 of ,{3'H5} ? In order to check for the SFD 1101 0101 isnt that 3 of {3'H5} will suffice for coding in RMII?
On Mon, Dec 24, 2018 at 3:52 PM jrrk [email protected] wrote:
In this case the coding is RMII, so it is checking two data bits and receive enable.
Sent from my iPhone
On 24 Dec 2018, at 05:39, clare7 [email protected] wrote:
Hi, I'm wondering what does the value {3'H7,{7{3'H5}}} indicates? It was found in Line 98
if ((rx_nxt == {3'H7,{7{3'H5}}}) && (byte_sync == 0) && (sync == 0))Based on the codes given, it seems like is checking the end of 8th (collected) RX packets which each packet is 3 bits size. However, I couldnt figure out the how did it comes to value H7 and H5?— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub, or mute the thread.
— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub < https://github.com/lowRISC/lowrisc-chip/issues/102#issuecomment-449698888 , or mute the thread < https://github.com/notifications/unsubscribe-auth/AcHzHLYMMmp5XSBN3x3VVofBZyYui36Pks5u8Ie5gaJpZM4ZgJRm
.
-- Regards, Ming — You are receiving this because you commented. Reply to this email directly, view it on GitHub, or mute the thread.
— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/lowRISC/lowrisc-chip/issues/102#issuecomment-449960842, or mute the thread https://github.com/notifications/unsubscribe-auth/AcHzHCUjAyK87XaO5V1-ASXD8PRTIMpmks5u821egaJpZM4ZgJRm .
-- Regards, Ming
You did. The port input_axis_tready of axis_gmii_tx.v is actually an output despite its name.
This indicates in a convoluted way when the transmitter is ready for more input. If you have
issues with the coding style you could take it up with the original author but I would advise
against this because we have a phrase 'Don't look a gift horse in the mouth'.
This is entirely contradictory to the Trojan horse saying 'Beware of Greeks bearing gift [horses]'.
So you decide if you received a gift horse or trojan horse, that's what open source is all about!
In the same way you can judge this overall release to see if it more closely fits the description
'many hands make light work' or 'too many cooks spoil the broth'.
Either way, have a prosperous New Year.
On 28/12/2018 07:13, clare7 wrote:
Noted. Thank you. I also notice that there is no signal that triggers *tx_axis_tready . *Did I miss out something?
if (tx_axis_tready) begin tx_frame_addr <= tx_frame_addr + 1; tx_axis_tlast <= (tx_frame_addr == tx_packet_length-2) & tx_axis_tvalid_dly; end
On Wed, Dec 26, 2018 at 8:36 PM jrrk [email protected] wrote:
You could certainly adapt the code to only check a single byte but thereby the chance of a false sync could be increased. Bearing in mind the chance of a bit error is greater early on in the packet due to the possibility of contention from multiple transmitters.
Sent from my iPhone
On 26 Dec 2018, at 04:56, clare7 [email protected] wrote:
In that case, why does it has to be 7 of ,{3'H5} ? In order to check for the SFD 1101 0101 isnt that 3 of {3'H5} will suffice for coding in RMII?
On Mon, Dec 24, 2018 at 3:52 PM jrrk [email protected] wrote:
In this case the coding is RMII, so it is checking two data bits and receive enable.
Sent from my iPhone
On 24 Dec 2018, at 05:39, clare7 [email protected] wrote:
Hi, I'm wondering what does the value {3'H7,{7{3'H5}}} indicates? It was found in Line 98
if ((rx_nxt == {3'H7,{7{3'H5}}}) && (byte_sync == 0) && (sync == 0))Based on the codes given, it seems like is checking the end of 8th (collected) RX packets which each packet is 3 bits size. However, I couldnt figure out the how did it comes to value H7 and H5?— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub, or mute the thread.
— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <
https://github.com/lowRISC/lowrisc-chip/issues/102#issuecomment-449698888
,
or mute the thread <
https://github.com/notifications/unsubscribe-auth/AcHzHLYMMmp5XSBN3x3VVofBZyYui36Pks5u8Ie5gaJpZM4ZgJRm
.
-- Regards, Ming — You are receiving this because you commented. Reply to this email directly, view it on GitHub, or mute the thread.
— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub
https://github.com/lowRISC/lowrisc-chip/issues/102#issuecomment-449960842,
or mute the thread
.
-- Regards, Ming
— You are receiving this because you commented. Reply to this email directly, view it on GitHub https://github.com/lowRISC/lowrisc-chip/issues/102#issuecomment-450305069, or mute the thread https://github.com/notifications/unsubscribe-auth/AAgF17qEA162oD37qy975gbuDXwRjt_yks5u9cSqgaJpZM4ZgJRm.