Synthesis of Duplicate Imports

[chuckb]

I have a design where I have imported 2 projects that use common custom circuits. The design simulates and executes ok. When I synthesize the design, I get '"XXXXXX". This is not allowed, please make sure all sheets have a unique name'. The board is set to use Vivado (if that matters). Question - is this by design? If so, it limits the utility of reusable components...is there a workaround?

This seems like a limitation that could be avoided if the DRC looked to see if the circuits are identical (and/or imported) and only generated the one definition.

[maehne]

Indeed, the scenario you describe, where the same .circ file gets included multiple times is known to be problematic. This functionality comes from the original Logisim code base and we haven't been able yet to fix it in such a way that it works reliably in all cases. Therefore, @BFH-ktt1 implemented the "File -> Merge..." function, which gives more predictable results. We recommend our students in group projects to work on their parts in independent .circ files and then to merge the new blocks into another .circ for integration. This can be done repeatedly and Logisim-evolution will ask whether to overwrite an existing circuit. Help improving this situation is welcome.