Arch-Notes

My short notes for CMU 18-447 Introduction to Computer Architecture – Spring 2015 (lectured by Prof. Onur Mutlu).
All the lecture materials (including lecture videos) are available on its course page.

Table of Contents

• L01. Introduction and Basics
• L02. Fundamental Concepts and ISA
• L03. ISA Tradeoffs

Previewed, In-progress

• L04. ISA Tradeoffs (cont.) & MIPS ISA
• L05. Intro to Microarchitecture: Single-Cycle*
• L06. Multi-Cycle and Microprogrammed Microarchitectures
• L09. Branch Prediction I
• L14. SIMD Processing (Vector and Array Processors)
• L18. Caches, Caches, Caches

Lecture Notes

L01. Introduction and Basics

• Denial of memory service (matlab vs gcc): cache locality, fairness problem, row buffer miss
• DRAM refresh: profile, more frequent refreshes for weaker rows
• Disturbance effects: all memories, aggressor/victim row, error correction mechanisms

L02. Fundamental Concepts and ISA

• 
• Architecture today: every component is being reevaluated
• 3 key components: Computation, Communication and Storage
• Storage: Memory (non-persistent storage like DRAM, persistent storage like flash memory) and Storage system (emerging technologies getting closer to DRAMs).
• Von Neumann model: control flow order (specified by instruction pointer)
• Dataflow model: data flow order (fired when its operands are ready, no instruction pointer)
• Dataflow nodes: conditional (branching), relational, barrier synchronization (parallel programs)
• ISA: agreed upon interface between software and hardware
• Microarchitecture: a specific implementation of ISA, not visible to software
• Microprocessor: ISA, uarch, circuits
• "Architecture"* = ISA + microarchitecture
• ISA = car functions (turn, acceleration/deceleration). Microarchitecture = how car manufacturers implement the functions underneath.
• 

L03. ISA Tradeoffs

• Bit steering: A bit to determine the type of instruction for interpretation
• Instruction: opcode, operands
• ISA elements:
  • Instruction sequencing model (control flow vs. data flow)
  • Instruction processing style (0, 1, 2, 3 address machines)
  • Instructions
  • Data types
  • Memory organization (Address space, Addressability)
  • Registers
  • Load/store (only on registers, RISC, ARM) vs. memory/memory architectures (CISC, x86)
• Addressing modes: how to describe memory address. More = better for programmers.
• Orthogonal ISA: (No. of addr modes) * (No. of opcodes) * (No. of data types)
• More ISA elements:
  • Privilege modes (permission)
  • Exception and interrupt handling
  • Virtual memory (virtual memory space > physical)
  • Access Protection
• CISC (Complex) vs. RISC (Reduced)

• Number of registers: More => better utilization and optimization, larger instruction size (more bits for addr)

License

CC Attribution-Share Alike 3.0 Unported