CLB in corners causes assertion failure

[rockybulwinkle]

Describe the bug When I create an FPGA layout with I/O in the center instead of around the edge, and set the corners to CLB, an assertion fails in openfpga/src/fabric/module_manager.cpp. Below is the message from openfpgashell.log:

/projects/current/OpenFPGA/svn_workAreas/rocky/old/openfpga_old/openfpga/src/fabric/module_manager.cpp:749 add_configurable_child: Assertion 'child_instance < num_instance(parent_module, child_module)' failed.

A clear and concise description of what the bug is. [X] OpenFPGA flow

To Reproduce

1. Apply the provided patch. It modifies the generate_fabric test to create an 8x8 grid filled with CLB and with the center 2x2 set to i/o.
2. Run the basic_tests/generate_bitstream task
3. Note, if I add <corners type="EMPTY" priority="101"/> to my layout, the run succeeds.

Patch:

index 467cac0c..b4307677 100644
--- a/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
diff --git a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf
index 958c8b9e..273b3e90 100644
--- a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf
@@ -24,6 +24,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
 # This is designed to allow the test case 'basic_tests/generate_testbench'
 # to use the Verilog netlists along with testbenches in HDL simulation
 openfpga_verilog_output_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH
+openfpga_vpr_device_layout=8x8
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
index 44235452..7ffd373a 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
@@ -91,6 +91,17 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
+    <fixed_layout name="8x8" width="8" height="8">
+      <!--'io' in center'-->
+      <single type="io" x="3" y="3" priority="20"/>
+      <single type="io" x="3" y="4" priority="20"/>
+      <single type="io" x="4" y="3" priority="20"/>
+      <single type="io" x="4" y="4" priority="20"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+
+    </fixed_layout>
+
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 

Expected behavior I expect to get a netlist of the described layout.

Enviornment (please complete the following information):

• OS:

• [X] Others. If so, please specify: Alma Linux 8.5

• Compiler:

• [X] gcc-8 Compiler version is Red Hat 8.5.0-4 specifically.

• Version:

• [X] Current master (4a1a1b503d317254e940d8d7c184ed7f5cd0b7bf as of writing this)

[tangxifan]

@rockybulwinkle Would you mind to check the architecture using VPR's GUI? It seems to me an architecture containing I/Os in the center of FPGAs.