Vpr integration

[Yitian4Debug]

Motivate of the pull request

• [ ] To address an existing issue. If so, please provide a link to the issue:
• [X] Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

• Currently, OpenFPGA has the following limitations:
  • VPR is not synced to latest version in VTR
  • Tileable rr graph is put under OpenFPGA/vpr but not merged back to VTR/vpr

What does this pull request change?

• This PR improves in the following aspects:
  • Sync up vpr to latest VTR/vpr
  • Sync up libs to latest VTR/libs
  • Move tileable rr graph to OpenFPGA/libopenfpga/libopenfpgatileablerrgraph

Which part of the code base require a change

• [X] VPR
• [X] Tileable routing architecture generator
• [X] OpenFPGA libraries
• [ ] FPGA-Verilog
• [ ] FPGA-Bitstream
• [ ] FPGA-SDC
• [ ] FPGA-SPICE
• [ ] Flow scripts
• [ ] Architecture library
• [ ] Cell library
• [ ] Documentation
• [ ] Regression tests
• [ ] Continous Integration (CI) scripts

Impact of the pull request

• [X] Require a change on Quality of Results (QoR)
• [X] Break back-compatibility. If so, please list who may be influenced.