Using 22nm Architectures

[Iripi97]

I am trying to use a 22nm architecture/feature size for my OpenFPGA project; however I am unable to find the 22nm architecture files (.XML). I can easily find the files required for Power analysis (in OpenFPGA/openfpga_flow/tech/PTM_22nm) with the 22nm feature size, however I cannot find the architecture files for 22nm in either /OpenFpga/openfpga_flow/openfpga_arch or in /OpenFPGA/openfpga_flow/vpr_arch.

Are there any 22nm sample .XML files (both for the openfpga_arch AND vpr_arch directories) that could be added to the repository, or linked in a comment below?

[tangxifan]

@Iripi97 Currently, we do not have any example architecture using a 22nm technology. However, OpenFPGA offers you high flexibility when porting an architecture from a technology to another. Please checkout the tutorial https://openfpga.readthedocs.io/en/master/tutorials/arch_modeling/open_cell_libraries_tutorial/, with which you can adapot existing examples to a 22nm technology.

[Iripi97]

@tangxifan I have already seen this tutorial. It is extremely helpful for understanding when to use different cell libraries. However at the moment, I do not have access to 22nm XML files, so realistically the main thing I am trying to change in files like k4_N4_40nm.xml or k4_N4_tileable_40nm.xml is the Vdd, chan_length, min_width, etc... essentially values that relate to the objects sizes/power that are declared in the .xml files. Realistically I am fine with just using the standard cell library, I just want to make sure the fabric is being accurately modeled size/power wise for 22nm. Also does one just need to modify the task.config file for the task to ensure PPA numbers are generated? Also where are these numbers generated in the contexts of the OpenFPGA workspace? Is it within the directory that houses the current task's related files/configurations?

[tangxifan]

@Iripi97

I do not have access to 22nm XML files, so realistically the main thing I am trying to change in files like k4_N4_40nm.xml or k4_N4_tileable_40nm.xml is the Vdd, chan_length, min_width, etc... essentially values that relate to the objects sizes/power that are declared in the .xml files.

• The Vdd, chan_length, min_width are parameters required by FPGA-SPICE. If you do not care FPGA-SPICE, you can give dummy numbers, FPGA-Verilog and FPGA-Bitstream should work fine.

Realistically I am fine with just using the standard cell library, I just want to make sure the fabric is being accurately modeled size/power wise for 22nm. Also does one just need to modify the task.config file for the task to ensure PPA numbers are generated? Realistically I am fine with just using the standard cell library, I just want to make sure the fabric is being accurately modeled size/power wise for 22nm. Also does one just need to modify the task.config file for the task to ensure PPA numbers are generated?

• In general, it is chip designers' responsibility to guarantee the correct PPA numbers in FPGA architecture description. It means that you need to run some timing analysis using ASIC tools, e.g., Synopsys PrimeTime or Synopsys HSPICE, and then you annotate the timing values to VPR architecture XML. As a result, your FPGA architecture reflects the correct timing of your chip.

You may consider to post such question on the discussion forum. Since this is more like a topic to discuss.

[Iripi97]

@tangxifan Thank you for your responses, they are helpful. Just one more question that I would love some clarification on: In my task.conf file I have the parameters power_analysis, spice_output, verilog_output all set to true (as well as power_tech_file pointing to appropriate XML file) but I am failing to generate (or see where it is generated) Power results. I can see the timing and area results in vpr_stat.out. Is this where Power results should be found, or is it typically generated in another file?

[tangxifan]

@Iripi97 Power analysis of VPR is enabled by adding options --power to your openfpga shell script when calling vpr. Currently, there is no such example in OpenFPGA's repo now. But it is very easy to do.

• You can check the VTR documentation at https://docs.verilogtorouting.org/en/latest/vpr/command_line_usage/?highlight=power#power-estimation-options
• Update your openfpga shell script by adding the options to the line where we call VPR. For example: https://github.com/lnis-uofu/OpenFPGA/blob/1603c9b40413a4256c7718b72d0cb40183bfb88b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga#L3
• Run the openfpga flow, the power results are stored in a separated file under postfix .power

[Iripi97]

@tangxifan When attempting power analysis I get the following: Error opening c17.act for r access: No such file or directory. From what I understand when using the VTR flow when instantiating a task/run it will automatically (as a part of its script) run ABC -> ACE -> to generate the activity file required for VPR power analysis. However this is not completed when enabling power options in the task.conf and calling the appropriate options with the vpr command within the script that is called by the run/task. Is there any assistance you could offer on how to fix this? Or potentially run the ABC, ACE tools manually to generate the activity file?

[tangxifan]

@Iripi97 If you turn on power analysis options in the task configuration file, ACE will be called.

https://github.com/lnis-uofu/OpenFPGA/blob/5e912b3c5113bf6be3ed29563e922b6791f70896/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf#L12

[Iripi97]

@tangxifan I do not believe the OpenFPGA tool has been set up properly for power analysis. I have run my benchmarks many times: (Attempt 1) I ran with power_analysis = true and no declaration of '--power' with VPR [in the OpenFPGA shell script]: the benchmarks run fine and all compile with OpenFPGA however there are NO power results (example.power files). (Attempt 2) I ran again with power_analysis = true and then a declaration of '--power' with VPR and again receive the error: vtr_util.cpp:253 Error opening file example.act for r access: No such file or directory. However I noticed that when looking through the contents of the run, there is an example.out.act file. Is it possible that OpenFPGA is just incorrectly naming the file/ searching for the wrong file name. Is this is easy fix within the C++ file vtr_util.cpp?

[tangxifan]

@Iripi97 For power analysis, you need

• enable --power option
• provide a tech property file (.xml)
• provide a signal activity file (.act)

Please read the VTR documentation https://docs.verilogtorouting.org/en/latest/vtr/power_estimation/#vpr

[tangxifan]

Close the issue as answered. If you need further help, please comment (reopen this issue) or create a new issue. Thank you for the interests in OpenFPGA.