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ValueTracking: Handle amdgcn_log in computeKnownFPClass
-
#172492
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#172491
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@llvm/pr-subscribers-llvm-analysis @llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Full diff: https://github.com/llvm/llvm-project/pull/172492.diff
2 Files Affected:
- (modified) llvm/lib/Analysis/ValueTracking.cpp (+7-4)
- (modified) llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-log.ll (+48-48)
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 045cbab221ac3..b2dba365a2dce 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -5399,7 +5399,8 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts,
case Intrinsic::log2:
case Intrinsic::experimental_constrained_log:
case Intrinsic::experimental_constrained_log10:
- case Intrinsic::experimental_constrained_log2: {
+ case Intrinsic::experimental_constrained_log2:
+ case Intrinsic::amdgcn_log: {
// log(+inf) -> +inf
// log([+-]0.0) -> -inf
// log(-inf) -> nan
@@ -5423,13 +5424,15 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts,
if (KnownSrc.isKnownNeverNaN() && KnownSrc.cannotBeOrderedLessThanZero())
Known.knownNot(fcNan);
- const Function *F = II->getFunction();
+ Type *EltTy = II->getType()->getScalarType();
+ if (IID == Intrinsic::amdgcn_log && EltTy->isFloatTy())
+ Known.knownNot(fcSubnormal);
+ const Function *F = II->getFunction();
if (!F)
break;
- const fltSemantics &FltSem =
- II->getType()->getScalarType()->getFltSemantics();
+ const fltSemantics &FltSem = EltTy->getFltSemantics();
DenormalMode Mode = F->getDenormalMode(FltSem);
if (KnownSrc.isKnownNeverLogicalZero(Mode))
diff --git a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-log.ll b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-log.ll
index 9040030787baf..35594fd9c8d16 100644
--- a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-log.ll
+++ b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-log.ll
@@ -12,9 +12,9 @@ define half @ret_log_f16(half %arg) #1 {
}
define float @ret_log_f32(float %arg) #1 {
-; CHECK-LABEL: define float @ret_log_f32(
+; CHECK-LABEL: define nofpclass(sub) float @ret_log_f32(
; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(sub) float @llvm.amdgcn.log.f32(float [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -22,9 +22,9 @@ define float @ret_log_f32(float %arg) #1 {
}
define float @ret_log_noinf(float nofpclass(inf) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_noinf(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_noinf(
; CHECK-SAME: float nofpclass(inf) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -32,9 +32,9 @@ define float @ret_log_noinf(float nofpclass(inf) %arg) #1 {
}
define float @ret_log_noneg(float nofpclass(ninf nsub nnorm) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_noneg(
+; CHECK-LABEL: define nofpclass(sub) float @ret_log_noneg(
; CHECK-SAME: float nofpclass(ninf nsub nnorm) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(ninf nsub nnorm) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(sub) float @llvm.amdgcn.log.f32(float nofpclass(ninf nsub nnorm) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -42,9 +42,9 @@ define float @ret_log_noneg(float nofpclass(ninf nsub nnorm) %arg) #1 {
}
define float @ret_log_noneg_nonan(float nofpclass(nan ninf nsub nnorm) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_noneg_nonan(
+; CHECK-LABEL: define nofpclass(nan sub) float @ret_log_noneg_nonan(
; CHECK-SAME: float nofpclass(nan ninf nsub nnorm) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(nan ninf nsub nnorm) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(nan sub) float @llvm.amdgcn.log.f32(float nofpclass(nan ninf nsub nnorm) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -52,9 +52,9 @@ define float @ret_log_noneg_nonan(float nofpclass(nan ninf nsub nnorm) %arg) #1
}
define float @ret_log_noinf_noneg(float nofpclass(inf nsub nnorm) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_noinf_noneg(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_noinf_noneg(
; CHECK-SAME: float nofpclass(inf nsub nnorm) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf nsub nnorm) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf nsub nnorm) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -62,9 +62,9 @@ define float @ret_log_noinf_noneg(float nofpclass(inf nsub nnorm) %arg) #1 {
}
define float @ret_log_noinf_noneg_nonan(float nofpclass(nan inf nsub nnorm) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_noinf_noneg_nonan(
+; CHECK-LABEL: define nofpclass(nan pinf sub) float @ret_log_noinf_noneg_nonan(
; CHECK-SAME: float nofpclass(nan inf nsub nnorm) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(nan inf nsub nnorm) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(nan pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(nan inf nsub nnorm) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -72,9 +72,9 @@ define float @ret_log_noinf_noneg_nonan(float nofpclass(nan inf nsub nnorm) %arg
}
define float @ret_log_nopinf(float nofpclass(pinf) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_nopinf(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_nopinf(
; CHECK-SAME: float nofpclass(pinf) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(pinf) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(pinf) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -82,9 +82,9 @@ define float @ret_log_nopinf(float nofpclass(pinf) %arg) #1 {
}
define float @ret_log_noninf(float nofpclass(ninf) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_noninf(
+; CHECK-LABEL: define nofpclass(sub) float @ret_log_noninf(
; CHECK-SAME: float nofpclass(ninf) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(ninf) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(sub) float @llvm.amdgcn.log.f32(float nofpclass(ninf) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -92,9 +92,9 @@ define float @ret_log_noninf(float nofpclass(ninf) %arg) #1 {
}
define float @ret_log_nonan(float nofpclass(nan) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_nonan(
+; CHECK-LABEL: define nofpclass(sub) float @ret_log_nonan(
; CHECK-SAME: float nofpclass(nan) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(nan) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(sub) float @llvm.amdgcn.log.f32(float nofpclass(nan) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -102,9 +102,9 @@ define float @ret_log_nonan(float nofpclass(nan) %arg) #1 {
}
define float @ret_log_nonan_noinf(float nofpclass(nan inf) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_nonan_noinf(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_nonan_noinf(
; CHECK-SAME: float nofpclass(nan inf) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(nan inf) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(nan inf) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -112,9 +112,9 @@ define float @ret_log_nonan_noinf(float nofpclass(nan inf) %arg) #1 {
}
define float @ret_log_nonan_noinf_nozero(float nofpclass(nan inf zero) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_nonan_noinf_nozero(
+; CHECK-LABEL: define nofpclass(inf sub) float @ret_log_nonan_noinf_nozero(
; CHECK-SAME: float nofpclass(nan inf zero) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(nan inf zero) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(inf sub) float @llvm.amdgcn.log.f32(float nofpclass(nan inf zero) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -122,9 +122,9 @@ define float @ret_log_nonan_noinf_nozero(float nofpclass(nan inf zero) %arg) #1
}
define float @ret_log_noinf_nozero(float nofpclass(inf zero) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_noinf_nozero(
+; CHECK-LABEL: define nofpclass(inf sub) float @ret_log_noinf_nozero(
; CHECK-SAME: float nofpclass(inf zero) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf zero) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(inf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf zero) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -132,9 +132,9 @@ define float @ret_log_noinf_nozero(float nofpclass(inf zero) %arg) #1 {
}
define float @ret_log_noinf_nonegzero(float nofpclass(inf nzero) %arg) #1 {
-; CHECK-LABEL: define float @ret_log_noinf_nonegzero(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_noinf_nonegzero(
; CHECK-SAME: float nofpclass(inf nzero) [[ARG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf nzero) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf nzero) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -142,10 +142,10 @@ define float @ret_log_noinf_nonegzero(float nofpclass(inf nzero) %arg) #1 {
}
define float @ret_log_positive_source(i32 %arg) #1 {
-; CHECK-LABEL: define float @ret_log_positive_source(
+; CHECK-LABEL: define nofpclass(nan pinf sub) float @ret_log_positive_source(
; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[UITOFP:%.*]] = uitofp i32 [[ARG]] to float
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float [[UITOFP]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(nan pinf sub) float @llvm.amdgcn.log.f32(float [[UITOFP]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%uitofp = uitofp i32 %arg to float
@@ -154,10 +154,10 @@ define float @ret_log_positive_source(i32 %arg) #1 {
}
define float @ret_log_unknown_sign(float nofpclass(nan) %arg, float nofpclass(nan) %arg1) #1 {
-; CHECK-LABEL: define float @ret_log_unknown_sign(
+; CHECK-LABEL: define nofpclass(sub) float @ret_log_unknown_sign(
; CHECK-SAME: float nofpclass(nan) [[ARG:%.*]], float nofpclass(nan) [[ARG1:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[UNKNOWN_SIGN_NOT_NAN:%.*]] = fmul nnan float [[ARG]], [[ARG1]]
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float [[UNKNOWN_SIGN_NOT_NAN]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(sub) float @llvm.amdgcn.log.f32(float [[UNKNOWN_SIGN_NOT_NAN]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%unknown.sign.not.nan = fmul nnan float %arg, %arg1
@@ -166,9 +166,9 @@ define float @ret_log_unknown_sign(float nofpclass(nan) %arg, float nofpclass(na
}
define float @ret_log_daz_noinf_nozero(float nofpclass(inf zero) %arg) #2 {
-; CHECK-LABEL: define float @ret_log_daz_noinf_nozero(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_daz_noinf_nozero(
; CHECK-SAME: float nofpclass(inf zero) [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf zero) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf zero) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -186,9 +186,9 @@ define <2 x float> @ret_log_daz_noinf_nozero_v2f32(<2 x float> nofpclass(inf zer
}
define float @ret_log_daz_noinf_nonegzero(float nofpclass(inf nzero) %arg) #2 {
-; CHECK-LABEL: define float @ret_log_daz_noinf_nonegzero(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_daz_noinf_nonegzero(
; CHECK-SAME: float nofpclass(inf nzero) [[ARG:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf nzero) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf nzero) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -196,9 +196,9 @@ define float @ret_log_daz_noinf_nonegzero(float nofpclass(inf nzero) %arg) #2 {
}
define float @ret_log_dynamic_noinf_nozero(float nofpclass(inf zero) %arg) #3 {
-; CHECK-LABEL: define float @ret_log_dynamic_noinf_nozero(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_dynamic_noinf_nozero(
; CHECK-SAME: float nofpclass(inf zero) [[ARG:%.*]]) #[[ATTR2:[0-9]+]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf zero) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf zero) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -206,9 +206,9 @@ define float @ret_log_dynamic_noinf_nozero(float nofpclass(inf zero) %arg) #3 {
}
define float @ret_log_dynamic_noinf_nonegzero(float nofpclass(inf nzero) %arg) #3 {
-; CHECK-LABEL: define float @ret_log_dynamic_noinf_nonegzero(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_dynamic_noinf_nonegzero(
; CHECK-SAME: float nofpclass(inf nzero) [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf nzero) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf nzero) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -216,9 +216,9 @@ define float @ret_log_dynamic_noinf_nonegzero(float nofpclass(inf nzero) %arg) #
}
define float @ret_log_ftz_noinf_nonegzero(float nofpclass(inf nzero) %arg) #4 {
-; CHECK-LABEL: define float @ret_log_ftz_noinf_nonegzero(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_ftz_noinf_nonegzero(
; CHECK-SAME: float nofpclass(inf nzero) [[ARG:%.*]]) #[[ATTR3:[0-9]+]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf nzero) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf nzero) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -226,9 +226,9 @@ define float @ret_log_ftz_noinf_nonegzero(float nofpclass(inf nzero) %arg) #4 {
}
define float @ret_log_ftz_dynamic_noinf_nonegzero(float nofpclass(inf nzero) %arg) #5 {
-; CHECK-LABEL: define float @ret_log_ftz_dynamic_noinf_nonegzero(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_ftz_dynamic_noinf_nonegzero(
; CHECK-SAME: float nofpclass(inf nzero) [[ARG:%.*]]) #[[ATTR4:[0-9]+]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf nzero) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf nzero) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -236,9 +236,9 @@ define float @ret_log_ftz_dynamic_noinf_nonegzero(float nofpclass(inf nzero) %ar
}
define float @ret_log_dynamic_noinf_nozero_nosub(float nofpclass(inf zero sub) %arg) #3 {
-; CHECK-LABEL: define float @ret_log_dynamic_noinf_nozero_nosub(
+; CHECK-LABEL: define nofpclass(inf sub) float @ret_log_dynamic_noinf_nozero_nosub(
; CHECK-SAME: float nofpclass(inf zero sub) [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf zero sub) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(inf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf zero sub) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -246,9 +246,9 @@ define float @ret_log_dynamic_noinf_nozero_nosub(float nofpclass(inf zero sub) %
}
define float @ret_log_dynamic_noinf_nopzero_nopsub(float nofpclass(inf pzero psub) %arg) #3 {
-; CHECK-LABEL: define float @ret_log_dynamic_noinf_nopzero_nopsub(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_dynamic_noinf_nopzero_nopsub(
; CHECK-SAME: float nofpclass(inf pzero psub) [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf pzero psub) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf pzero psub) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
@@ -256,9 +256,9 @@ define float @ret_log_dynamic_noinf_nopzero_nopsub(float nofpclass(inf pzero psu
}
define float @ret_log_dynamic_noinf_nonzero_nonsub(float nofpclass(inf nzero nsub) %arg) #3 {
-; CHECK-LABEL: define float @ret_log_dynamic_noinf_nonzero_nonsub(
+; CHECK-LABEL: define nofpclass(pinf sub) float @ret_log_dynamic_noinf_nonzero_nonsub(
; CHECK-SAME: float nofpclass(inf nzero nsub) [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.amdgcn.log.f32(float nofpclass(inf nzero nsub) [[ARG]]) #[[ATTR7]]
+; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(pinf sub) float @llvm.amdgcn.log.f32(float nofpclass(inf nzero nsub) [[ARG]]) #[[ATTR7]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.amdgcn.log.f32(float %arg)
:penguin: Linux x64 Test Results
- 167263 tests passed
- 2955 tests skipped
- 1 test failed
Failed Tests
(click on a test name to see its output)
MLIR
MLIR.Dialect/XeGPU/propagate-layout-subgroup.mlir (Likely Already Failing)
This test is already failing at the base commit.Exit Code: 1
Command Output (stdout):
--
# RUN: at line 1
/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/mlir-opt -xevm-attach-target='chip=pvc' -xegpu-propagate-layout="layout-kind=subgroup" -split-input-file /home/gha/actions-runner/_work/llvm-project/llvm-project/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir | /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/FileCheck /home/gha/actions-runner/_work/llvm-project/llvm-project/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
# executed command: /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/mlir-opt -xevm-attach-target=chip=pvc -xegpu-propagate-layout=layout-kind=subgroup -split-input-file /home/gha/actions-runner/_work/llvm-project/llvm-project/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
# note: command had no output on stdout or stderr
# executed command: /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/FileCheck /home/gha/actions-runner/_work/llvm-project/llvm-project/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
# .---command stderr------------
# | /home/gha/actions-runner/_work/llvm-project/llvm-project/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir:10:17: error: CHECK-SAME: expected string not found in input
# | // CHECK-SAME: {layout_result_0 = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>}
# | ^
# | <stdin>:5:90: note: scanning from here
# | %1 = xegpu.load_nd %0 <{layout = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>}> : !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>> -> vector<256x128xf32>
# | ^
# | <stdin>:6:17: note: possible intended match here
# | xegpu.store_nd %1, %0 <{layout = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>}> : vector<256x128xf32>, !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>>
# | ^
# | /home/gha/actions-runner/_work/llvm-project/llvm-project/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir:36:17: error: CHECK-SAME: expected string not found in input
# | // CHECK-SAME: {layout_result_0 = #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>} :
# | ^
# | <stdin>:18:112: note: scanning from here
# | %2 = xegpu.load_nd %0[0, 0] <{layout = #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>}> : !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>> -> vector<256x128xf32>
# | ^
# | <stdin>:19:35: note: possible intended match here
# | %3 = vector.transpose %2, [1, 0] {layout_result_0 = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 64], order = [1, 0]>} : vector<256x128xf32> to vector<128x256xf32>
# | ^
# |
# | Input file: <stdin>
# | Check file: /home/gha/actions-runner/_work/llvm-project/llvm-project/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
# |
# | -dump-input=help explains the following input dump.
# |
# | Input was:
# | <<<<<<
# | 1: module {
# | 2: gpu.module @test [#xevm.target<chip = "pvc">] {
# | 3: func.func @store_nd(%arg0: memref<256x128xf32>) {
# | 4: %0 = xegpu.create_nd_tdesc %arg0 : memref<256x128xf32> -> !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>>
# | 5: %1 = xegpu.load_nd %0 <{layout = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>}> : !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>> -> vector<256x128xf32>
# | same:10'0 X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
# | 6: xegpu.store_nd %1, %0 <{layout = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>}> : vector<256x128xf32>, !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>>
# | same:10'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | same:10'1 ? possible intended match
# | 7: return
# | same:10'0 ~~~~~~~~
# | 8: }
# | same:10'0 ~~~
# | 9: }
# | same:10'0 ~~~
# | 10: }
# | same:10'0 ~~
# | 11:
# | same:10'0 ~
# | 12: // -----
# | same:10'0 ~~~~~~~~~
# | 13: module {
# | same:10'0 ~~~~~~~~~
# | 14: gpu.module @test [#xevm.target<chip = "pvc">] {
# | same:10'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 15: func.func @vector_transpose(%arg0: memref<256x128xf32>, %arg1: memref<128x256xf32>) {
# | same:10'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 16: %0 = xegpu.create_nd_tdesc %arg0 : memref<256x128xf32> -> !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>>
# | 17: %1 = xegpu.create_nd_tdesc %arg1 : memref<128x256xf32> -> !xegpu.tensor_desc<128x256xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 64], order = [1, 0]>>
# | 18: %2 = xegpu.load_nd %0[0, 0] <{layout = #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>}> : !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>> -> vector<256x128xf32>
# | same:36'0 X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
# | 19: %3 = vector.transpose %2, [1, 0] {layout_result_0 = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 64], order = [1, 0]>} : vector<256x128xf32> to vector<128x256xf32>
# | same:36'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | same:36'1 ? possible intended match
# | 20: xegpu.store_nd %3, %1[0, 0] <{layout = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 64], order = [1, 0]>}> : vector<128x256xf32>, !xegpu.tensor_desc<128x256xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 64], order = [1, 0]>>
# | same:36'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 21: return
# | same:36'0 ~~~~~~~~
# | 22: }
# | same:36'0 ~~~
# | 23: }
# | same:36'0 ~~~
# | 24: }
# | same:36'0 ~~
# | 25:
# | same:36'0 ~
# | >>>>>>
# `-----------------------------
# error: command failed with exit status: 1
--
If these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the infrastructure label.
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:window: Windows x64 Test Results
- 128745 tests passed
- 2826 tests skipped
- 1 test failed
Failed Tests
(click on a test name to see its output)
MLIR
MLIR.Dialect/XeGPU/propagate-layout-subgroup.mlir
Exit Code: 1
Command Output (stdout):
--
# RUN: at line 1
c:\_work\llvm-project\llvm-project\build\bin\mlir-opt.exe -xevm-attach-target='chip=pvc' -xegpu-propagate-layout="layout-kind=subgroup" -split-input-file C:\_work\llvm-project\llvm-project\mlir\test\Dialect\XeGPU\propagate-layout-subgroup.mlir | c:\_work\llvm-project\llvm-project\build\bin\filecheck.exe C:\_work\llvm-project\llvm-project\mlir\test\Dialect\XeGPU\propagate-layout-subgroup.mlir
# executed command: 'c:\_work\llvm-project\llvm-project\build\bin\mlir-opt.exe' -xevm-attach-target=chip=pvc -xegpu-propagate-layout=layout-kind=subgroup -split-input-file 'C:\_work\llvm-project\llvm-project\mlir\test\Dialect\XeGPU\propagate-layout-subgroup.mlir'
# note: command had no output on stdout or stderr
# executed command: 'c:\_work\llvm-project\llvm-project\build\bin\filecheck.exe' 'C:\_work\llvm-project\llvm-project\mlir\test\Dialect\XeGPU\propagate-layout-subgroup.mlir'
# .---command stderr------------
# | C:\_work\llvm-project\llvm-project\mlir\test\Dialect\XeGPU\propagate-layout-subgroup.mlir:10:17: error: CHECK-SAME: expected string not found in input
# | // CHECK-SAME: {layout_result_0 = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>}
# | ^
# | <stdin>:5:90: note: scanning from here
# | %1 = xegpu.load_nd %0 <{layout = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>}> : !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>> -> vector<256x128xf32>
# | ^
# | <stdin>:6:17: note: possible intended match here
# | xegpu.store_nd %1, %0 <{layout = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>}> : vector<256x128xf32>, !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>>
# | ^
# | C:\_work\llvm-project\llvm-project\mlir\test\Dialect\XeGPU\propagate-layout-subgroup.mlir:36:17: error: CHECK-SAME: expected string not found in input
# | // CHECK-SAME: {layout_result_0 = #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>} :
# | ^
# | <stdin>:18:112: note: scanning from here
# | %2 = xegpu.load_nd %0[0, 0] <{layout = #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>}> : !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>> -> vector<256x128xf32>
# | ^
# | <stdin>:19:35: note: possible intended match here
# | %3 = vector.transpose %2, [1, 0] {layout_result_0 = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 64], order = [1, 0]>} : vector<256x128xf32> to vector<128x256xf32>
# | ^
# |
# | Input file: <stdin>
# | Check file: C:\_work\llvm-project\llvm-project\mlir\test\Dialect\XeGPU\propagate-layout-subgroup.mlir
# |
# | -dump-input=help explains the following input dump.
# |
# | Input was:
# | <<<<<<
# | 1: module {
# | 2: gpu.module @test [#xevm.target<chip = "pvc">] {
# | 3: func.func @store_nd(%arg0: memref<256x128xf32>) {
# | 4: %0 = xegpu.create_nd_tdesc %arg0 : memref<256x128xf32> -> !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>>
# | 5: %1 = xegpu.load_nd %0 <{layout = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>}> : !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>> -> vector<256x128xf32>
# | same:10'0 X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
# | 6: xegpu.store_nd %1, %0 <{layout = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>}> : vector<256x128xf32>, !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 32]>>
# | same:10'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | same:10'1 ? possible intended match
# | 7: return
# | same:10'0 ~~~~~~~~
# | 8: }
# | same:10'0 ~~~
# | 9: }
# | same:10'0 ~~~
# | 10: }
# | same:10'0 ~~
# | 11:
# | same:10'0 ~
# | 12: // -----
# | same:10'0 ~~~~~~~~~
# | 13: module {
# | same:10'0 ~~~~~~~~~
# | 14: gpu.module @test [#xevm.target<chip = "pvc">] {
# | same:10'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 15: func.func @vector_transpose(%arg0: memref<256x128xf32>, %arg1: memref<128x256xf32>) {
# | same:10'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 16: %0 = xegpu.create_nd_tdesc %arg0 : memref<256x128xf32> -> !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>>
# | 17: %1 = xegpu.create_nd_tdesc %arg1 : memref<128x256xf32> -> !xegpu.tensor_desc<128x256xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 64], order = [1, 0]>>
# | 18: %2 = xegpu.load_nd %0[0, 0] <{layout = #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>}> : !xegpu.tensor_desc<256x128xf32, #xegpu.layout<sg_layout = [4, 8], sg_data = [64, 32], order = [0, 1]>> -> vector<256x128xf32>
# | same:36'0 X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
# | 19: %3 = vector.transpose %2, [1, 0] {layout_result_0 = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 64], order = [1, 0]>} : vector<256x128xf32> to vector<128x256xf32>
# | same:36'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | same:36'1 ? possible intended match
# | 20: xegpu.store_nd %3, %1[0, 0] <{layout = #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 64], order = [1, 0]>}> : vector<128x256xf32>, !xegpu.tensor_desc<128x256xf32, #xegpu.layout<sg_layout = [8, 4], sg_data = [32, 64], order = [1, 0]>>
# | same:36'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 21: return
# | same:36'0 ~~~~~~~~
# | 22: }
# | same:36'0 ~~~
# | 23: }
# | same:36'0 ~~~
# | 24: }
# | same:36'0 ~~
# | 25:
# | same:36'0 ~
# | >>>>>>
# `-----------------------------
# error: command failed with exit status: 1
--
If these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the infrastructure label.