llvm-project
llvm-project copied to clipboard
llvm
[CIR][X86] Add support for alignd builtins
Thank you for submitting a Pull Request (PR) to the LLVM Project!
This PR will be automatically labeled and the relevant teams will be notified.
If you wish to, you can add reviewers by using the "Reviewers" section on this page.
If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using @ followed by their GitHub username.
If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers.
If you have further questions, they may be answered by the LLVM GitHub User Guide.
You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums.
![github-actions[bot] avatar](https://avatars.githubusercontent.com/in/15368?v=4 "Published by a pub.dev verified publisher"){kind=small}
@llvm/pr-subscribers-clang
Author: None (YGGkk)
Changes
Full diff: https://github.com/llvm/llvm-project/pull/171621.diff
2 Files Affected:
- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp (+20-3)
- (added) clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c (+55)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 62836ce0f7537..6b4e06966b828 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -1154,9 +1154,6 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
case X86::BI__builtin_ia32_palignr128:
case X86::BI__builtin_ia32_palignr256:
case X86::BI__builtin_ia32_palignr512:
- case X86::BI__builtin_ia32_alignd128:
- case X86::BI__builtin_ia32_alignd256:
- case X86::BI__builtin_ia32_alignd512:
case X86::BI__builtin_ia32_alignq128:
case X86::BI__builtin_ia32_alignq256:
case X86::BI__builtin_ia32_alignq512:
@@ -1182,6 +1179,26 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
std::string("unimplemented X86 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return {};
+ case X86::BI__builtin_ia32_alignd128:
+ case X86::BI__builtin_ia32_alignd256:
+ case X86::BI__builtin_ia32_alignd512: {
+ unsigned numElts = cast<cir::VectorType>(ops[0].getType()).getSize();
+ unsigned shiftVal =
+ ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue() &
+ 0xff;
+
+ // Mask the shift amount to width of a vector.
+ shiftVal &= numElts - 1;
+
+ SmallVector<mlir::Attribute, 16> indices;
+ mlir::Type i32Ty = builder.getSInt32Ty();
+ for (unsigned i = 0; i != numElts; ++i)
+ indices.push_back(
+ cir::IntAttr::get(i32Ty, i + shiftVal));
+
+ return builder.createVecShuffle(getLoc(expr->getExprLoc()), ops[0], ops[1],
+ indices);
+ }
case X86::BI__builtin_ia32_kshiftliqi:
case X86::BI__builtin_ia32_kshiftlihi:
case X86::BI__builtin_ia32_kshiftlisi:
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c
new file mode 100644
index 0000000000000..73c21d6f3d802
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c
@@ -0,0 +1,55 @@
+// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+
+#include <immintrin.h>
+
+__v4si test_builtin_ia32_alignd128()
+{
+ // CIR-LABEL: _builtin_ia32_alignd128
+ // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !s32i>
+
+ // LLVM-LABEL: test_builtin_ia32_alignd128
+ // LLVM: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+
+ // OGCG-LABEL: test_builtin_ia32_alignd128
+ // OGCG: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ __v4si vec1 = {0, 1, 2, 3};
+ __v4si vec2 = {4, 5, 6, 7};
+ return __builtin_ia32_alignd128(vec1, vec2, 0);
+}
+
+__v8si test_builtin_ia32_alignd256()
+{
+ // CIR-LABEL: _builtin_ia32_alignd256
+ // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !s32i>
+ // LLVM-LABEL: test_builtin_ia32_alignd256
+ // LLVM: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ // OGCG-LABEL: test_builtin_ia32_alignd256
+ // OGCG: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ __v8si vec1 = {0, 1, 2, 3, 4, 5, 6, 7};
+ __v8si vec2 = {8, 9, 10, 11, 12, 13, 14, 15};
+ return __builtin_ia32_alignd256(vec1, vec2, 0);
+}
+
+__v16si test_builtin_ia32_alignd512()
+{
+ // CIR-LABEL: _builtin_ia32_alignd512
+ // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<16 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i] : !cir.vector<16 x !s32i>
+ // LLVM-LABEL: test_builtin_ia32_alignd512
+ // LLVM: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ // OGCG-LABEL: test_builtin_ia32_alignd512
+ // OGCG: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ __v16si vec1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+ __v16si vec2 = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
+ return __builtin_ia32_alignd512(vec1, vec2, 0);
+}
\ No newline at end of file
@llvm/pr-subscribers-clangir
Author: None (YGGkk)
Changes
Full diff: https://github.com/llvm/llvm-project/pull/171621.diff
2 Files Affected:
- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp (+20-3)
- (added) clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c (+55)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 62836ce0f7537..6b4e06966b828 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -1154,9 +1154,6 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
case X86::BI__builtin_ia32_palignr128:
case X86::BI__builtin_ia32_palignr256:
case X86::BI__builtin_ia32_palignr512:
- case X86::BI__builtin_ia32_alignd128:
- case X86::BI__builtin_ia32_alignd256:
- case X86::BI__builtin_ia32_alignd512:
case X86::BI__builtin_ia32_alignq128:
case X86::BI__builtin_ia32_alignq256:
case X86::BI__builtin_ia32_alignq512:
@@ -1182,6 +1179,26 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
std::string("unimplemented X86 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return {};
+ case X86::BI__builtin_ia32_alignd128:
+ case X86::BI__builtin_ia32_alignd256:
+ case X86::BI__builtin_ia32_alignd512: {
+ unsigned numElts = cast<cir::VectorType>(ops[0].getType()).getSize();
+ unsigned shiftVal =
+ ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue() &
+ 0xff;
+
+ // Mask the shift amount to width of a vector.
+ shiftVal &= numElts - 1;
+
+ SmallVector<mlir::Attribute, 16> indices;
+ mlir::Type i32Ty = builder.getSInt32Ty();
+ for (unsigned i = 0; i != numElts; ++i)
+ indices.push_back(
+ cir::IntAttr::get(i32Ty, i + shiftVal));
+
+ return builder.createVecShuffle(getLoc(expr->getExprLoc()), ops[0], ops[1],
+ indices);
+ }
case X86::BI__builtin_ia32_kshiftliqi:
case X86::BI__builtin_ia32_kshiftlihi:
case X86::BI__builtin_ia32_kshiftlisi:
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c
new file mode 100644
index 0000000000000..73c21d6f3d802
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c
@@ -0,0 +1,55 @@
+// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+
+#include <immintrin.h>
+
+__v4si test_builtin_ia32_alignd128()
+{
+ // CIR-LABEL: _builtin_ia32_alignd128
+ // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !s32i>
+
+ // LLVM-LABEL: test_builtin_ia32_alignd128
+ // LLVM: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+
+ // OGCG-LABEL: test_builtin_ia32_alignd128
+ // OGCG: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ __v4si vec1 = {0, 1, 2, 3};
+ __v4si vec2 = {4, 5, 6, 7};
+ return __builtin_ia32_alignd128(vec1, vec2, 0);
+}
+
+__v8si test_builtin_ia32_alignd256()
+{
+ // CIR-LABEL: _builtin_ia32_alignd256
+ // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !s32i>
+ // LLVM-LABEL: test_builtin_ia32_alignd256
+ // LLVM: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ // OGCG-LABEL: test_builtin_ia32_alignd256
+ // OGCG: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ __v8si vec1 = {0, 1, 2, 3, 4, 5, 6, 7};
+ __v8si vec2 = {8, 9, 10, 11, 12, 13, 14, 15};
+ return __builtin_ia32_alignd256(vec1, vec2, 0);
+}
+
+__v16si test_builtin_ia32_alignd512()
+{
+ // CIR-LABEL: _builtin_ia32_alignd512
+ // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<16 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i] : !cir.vector<16 x !s32i>
+ // LLVM-LABEL: test_builtin_ia32_alignd512
+ // LLVM: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ // OGCG-LABEL: test_builtin_ia32_alignd512
+ // OGCG: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ __v16si vec1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+ __v16si vec2 = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
+ return __builtin_ia32_alignd512(vec1, vec2, 0);
+}
\ No newline at end of file
:penguin: Linux x64 Test Results
- 112977 tests passed
- 4096 tests skipped
:white_check_mark: The build succeeded and all tests passed.
Hi, @andykaylor, I'm confused why the workflows is blocked with this status the Build and Test is waiting
I'm confused why the workflows is blocked with this status the Build and Test is waiting
Don't worry, it just needs to be approved to run by a maintainer when you first submit a PR for llvm-project. I approved it.
@YGGkk Congratulations on having your first Pull Request (PR) merged into the LLVM Project!
Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR.
Please check whether problems have been caused by your change specifically, as the builds can include changes from many authors. It is not uncommon for your change to be included in a build that fails due to someone else's changes, or infrastructure issues.
How to do this, and the rest of the post-merge process, is covered in detail here.
If your change does cause a problem, it may be reverted, or you can revert it yourself. This is a normal part of LLVM development. You can fix your changes and open a new PR to merge them again.
If you don't get any reports, no action is required from you. Your changes are working as expected, well done!