circt
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Circuit IR Compilers and Tools
Add a conversion for the `moore.net` op to MooreToConv: https://chipsalliance.github.io/sv-tests-results/?v=circt_verilog+12.4+if
This is related to https://github.com/llvm/circt/issues/4886 in that this is sort of a special case. Fixing #4886 would fix this issue so long as infer-resets is followed by dedup (as it...
In the following FIRRTL, we have a module instantiated twice, once in a FullAsyncReset domain, and once not in any domain. ``` firrtl circuit Top : %[[ { "class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Top|FullAsyncWrapper>rf_reset"...
- [Arc][ArcCostModel]: Make th cost of arc.vectorize and arc.output zero - [Arc][Vectorization]: Add vector splitter
I think that IMDCE is not deleting instances of public modules, which should be allowed. Given the following test case: ```firrtl FIRRTL version 4.0.0 circuit Foo: public module Bar: public...
Could anyone provide guidance on how to represent the system function like `$urandom` in the IR? As I am not familiar with Chisel and FIRRTL, I am particularly interested in...
Probes can target the wrong signal when a local signal has the same name as the containing module. When given the following input, compiled with `firtool xmr.fir` we get the...
In T1 project, we have multiple configurations, e.g. with or without subsystem, each having different OM hierarchy (the top OM class will be `T1Subsystem_Class` or `T1_Class` respectively). @sequencer suggests we...
Consider: ```firrtl FIRRTL version 4.0.0 circuit Foo: public module Foo: mem memory: data-type => UInt depth => 8 reader => foo bar baz read-latency => 0 write-latency => 1 read-under-write...
Consider: ```firrtl FIRRTL version 4.0.0 circuit Foo: public module Foo: mem memory: depth => 8 reader => r read-latency => 0 write-latency => 1 read-under-write => undefined data-type => UInt...