circt
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llvm
Circuit IR Compilers and Tools
In Chisel we are seeking for intrinsics for sampled value functions like `$rose` and `$stable` to use with LTL and I think it should be lowered to the `sv` dialect...
The ProcessLowering pass checks whether an `llhd.process` operation is a combinational process and inlines it into the parent module if that's the case. However, it doesn't check for aliasing drives....
The current formal test interface can be picked up by the btor2 back-end, but not the `circt-bmc` backend. It would be nice to look into whether or not this conversion...
Currently we cannot verify LEC between following two modules: ``` hw.module @MultibitMux(in %a_0 : i1, in %a_1 : i1, in %sel : i1, out b : i1) { %0 =...
This adds a cast operation from normal type to immutable type.
Currently SeqToSv tests are scattered in `test/Dialect/Seq` but they should be put under `test/Conversion/SeqToSV`.
Consider: ```firrtl FIRRTL version 4.0.0 circuit Foo : layer L, bind : extmodule Bar : input a : Analog public module Foo : input a : Analog layerblock L: inst...
This pass performs firreg random initialization for seq.compreg. With this pass we can represent firreg initialization with compreg so we can eventually deprecate existing FirregLowering. There are still several differences:...
Add support for the `moore.pow*` ops in MooreToCore: https://chipsalliance.github.io/sv-tests-results/?v=circt_verilog+11.4.3+binary_op_pow
