circt
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llvm
Circuit IR Compilers and Tools
Both registers have a reset, although the first uses the `regreset` representation, and the latter uses a regular `reg` driven by a mux. ```firrtl FIRRTL version 4.0.0 circuit Foo: %[[...
Two identical modules, both annotated with FART: ```FIRRTL FIRRTL version 4.0.0 circuit Foo: %[[ {"class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Foo|Foo>r"}, {"class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Foo|Bar>r"} ]] public module Foo: input c : Clock input i : UInt...
```firrtl FIRRTL version 4.0.0 circuit Foo: %[[ { "class": "circt.FullResetAnnotation", "target": "~Foo|Foo>r", "resetType": "sync" } ]] public module Foo: input c : Clock input i : UInt input r :...
The original iteration of this bug was fixed in https://github.com/llvm/circt/pull/6912, but it appears that fix only works for registers in modules contain the wire or port marked with a `circt.FullResetAnnotation`,...
```firrtl FIRRTL version 4.0.0 circuit Foo: %[[ ]] public module Foo: input c : Clock input i0 : UInt input i1 : UInt input r : UInt output o0 :...
Breaking down #7409 This patch will support memory banking in Calyx by user specifying the number of available banks for each memory (in the order they are declared in the...
I introduced an interface for hardware contracts to the `verif` dialect. This should be exposed to FIRRTL so that we can access it via Chisel. Here is an idea of...
This transform is meant for dialects that inherently does not have a `switch` control statement (like Calyx)
Resolves https://github.com/llvm/circt/issues/7664
