circt
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llvm
Circuit IR Compilers and Tools
The current `scf` to `calyx` conversion handles `memref` arguments by directly inlining all the ports for the memory into the component's interface. Instead of doing this, we should use the...
WIP, tests and careful self-review still need to be done. Posting for visibility. Builds on #7137 (this is all unreachable after that PR).
This is still aspirational, converting modules and instances is still outstanding (no open PR). This describes what is happening in: #7117 , #7118 , #7119 , #7133
This is an attempt at reducing the conservativeness of the cross-block optimization barrier introduced in #6235. See also #6523. If canonicalization of an operation is prevented due to an operand...
This was removed in https://github.com/llvm/circt/pull/7129, because this requirement never existed in EmitOMIR, and in real designs coming from Chisel today, we are not yet able to enforce single instantiation. This...
Consider: ``` FIRRTL version 4.0.0 circuit ConstAlias: type X = { a: const UInt } public module ConstAlias: input x : X output y : X connect y, x ```...
This PR modifies the `verif::clocked_assertlike` ops to allow for the disable to be optional. In the case where it is omitted, it will be inferred from the property itself following...
There are a number of cool projects/ideas (Arc, ImportVerilog, SystemC, LEC, Model Checking, Synthesis, HLS, Rust bindings and so on) in CIRCT but I think currently it's not much visible...
This PR enables the SystemVerilog generated by Chisel&CIRCT can be `fwrite` to different files by the simulator. FIRRTL Spec changes: chipsalliance/firrtl-spec#213 (some discussion already there) Closes #7092, CC @seldridge @sequencer...
This patch stacks on #7086 . Add support for floating point addition in Calyx
