circt
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llvm
Circuit IR Compilers and Tools
Since the OM dialect's inception, fields were symbols in the Class. This was problematic, because Classes themselves are symbols in the builtin Module symbol table, so they can be referenced...
This PR changes VerbosePassInstrumentation to print timestamp along with logging message. ``` [2024-05-21 07:19:23:firtool] Running "firrtl-lower-open-aggs" [2024-05-21 07:19:23:firtool] -- Done in 0.000 sec [2024-05-21 07:19:23:firtool] Running "firrtl-resolve-paths" [2024-05-21 07:19:23:firtool] --...
The `arc.vectorize` op currently doesn't allow its body region to produce more than one result. This is a limitation in MLIR, which does not support VariadicOfVariadic results yet. VariadicOfVariadic operands...
The `arc.vectorize` op currently has no way of capturing if some of the vector lanes all have the exact same input operand. This is important for vectorizing `arc.state` ops which...
For right expression case, struct or union will also be read. For create case, the name will be SSA. Also delete some useless space in other code.
The motivation of this PR is to get a frontend/backend agnostic representation of "printf-like" format strings into the core dialects. These should allow us to specify the emission of messages...
In addition, add a new pass called `MergeAssignments` to merge the easy declaration and its value(continuous assignment) into a new op called `assigned_variable`. Don't handle `blocking_assign` and `nonBlocking_assign` due to...
