circt
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llvm
Circuit IR Compilers and Tools
### This PR implements a Proposal for FIRRTL XMR representation **Problem** How to express XMRs using ports in FIRRTL dialect. The ports can be removed during lowering and replaced with...
I was thinking something like: ```python @fsm.machine class F1: clk = Clock() go = Input(types.i1) valid = Input(types.i1) data = Input(types.i4) @fsm.state(initial=True) def a(ports, next): with If(ports.go): next.b() EndIf() @fsm.state...
This one may or may not be possible. I would like a CI pipeline which checks whether or not a commit broke pycde (runs the pycde tests). However, I do...
I would like some level of checking on each PR, but I _really_ don't want other changes (which may break us) to cause PR gates to fail for non-PyCDE developers.
- [ ] Document basics: modules, generators, system, ports, etc. - [ ] Document the Type and Value systems. Discuss the difference between Python values and PyCDE Values. - [...
https://docs.readthedocs.io/en/stable/tutorial/ To encourage us to write more documentation...
The `ChainedCast` pattern, introduced in https://github.com/llvm/circt/pull/3647, can produce wrong and illegal results, i.e.: ```mlir %0 = hwarith.cast %a : (ui8) -> (si8) %1 = hwarith.cast %0 : (si8) -> (si10)...
This issue serves as a tracking commit for implementing the remaining operations in `hwarith` - [ ] `hwarith.shl` - [ ] `hwarith.shr` (sign extending on `si` and zero extending on...
This is WIP to demonstrate how the pass can be extended to: * Extract wires and instances it knows are only used in the verification statements * Remove things that...
```scala circuit Foo: module Foo: input in1: UInt[2] input in2: UInt[2] input cond: UInt output o: UInt[2] when cond: o
