[ImportVerilog] moore.conversion generated instead of moore.int_to_string

[TaoBi22]

As pointed out by @Scheremo on #9199, the following SV snippet from sv-tests:

// Copyright (C) 2019-2021  The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier: ISC


/*
:name: string_len
:description: string.len()  tests
:tags: 6.16.1
*/
module top();
	string a = "Test";
	int b = a.len();
endmodule

produces a moore.conversion op from an int to string, but there's a dedicated moore.int_to_string op that we would expect to be materialized there instead

[TaoBi22]

The generated Moore IR is:

module {
  moore.module @top() {
    %0 = moore.constant_string "Test" : i32
    %1 = moore.conversion %0 : !moore.i32 -> !moore.string
    %a = moore.variable %1 : <string>
    %2 = moore.read %a : <string>
    %3 = moore.string.len %2
    moore.output
  }
}