Support for Adding Parameter Annotations to Generated Modules (e.g., as Comments)

[farukyld]

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Context

I'm using PyCDE to generate parameterized modules and test them using a handwritten Verilator testbench. To simplify the testbench logic, I instantiate different versions of the module under test using a single testbench. For that to work, all the modules must have the same top-level name.

To achieve this, I prefixed the module builder's argument with an underscore ("_"). With that, generated module's name doesn't contain parameters and is unified, but it creates another problem…

Problem

By removing the parameters from the module name, I lose visibility into what configuration a given module was generated from. This makes it difficult to track which parameters were used for which module, especially when dealing with multiple variations. As a result, debugging and traceability suffer.

Question/Feature Request

Is there a way to annotate the generated Verilog/SystemVerilog module with a comment that includes the parameter values? Ideally, I’d like to see something like this:

// Parameters: WIDTH=32, DEPTH=64
module my_module (...);

If this is already supported in PyCDE, could you provide an example of how to do it? If not, would it be feasible to add such a feature?

[teqdruid]

Sorry it took me so long to post here.

Turns out there is a property in hw.module to emit a comment above. So this is a simple feature addition. I was thinking that the docstring should be put above the module. WDYT?

[teqdruid]

Does it make sense to also add the module parameters? How about the metadata which you can optionally add?

[farukyld]

ı didn't tried yet but probably all your suggestions would work for me. ı want to add metadata/comment to generated verilog module (maybe wire, register,...). it doesnt have to derived automatically from parameters. maybe this is already possible but the problem is ı dont know how to achieve that. sorry for the overspecific issue title btw. I made an ai rephrase it.

[farukyld]

also ı want module names to unified, currently ı do it by prefixing the parameter with underscore. but this disturbs the parameter caching behavior.

[teqdruid]

also ı want module names to unified, currently ı do it by prefixing the parameter with underscore. but this disturbs the parameter caching behavior.

I forgot to reply. You can override the output module name for all modules, not just externs.

[farukyld]

thank you. if it is okay, you may close the issue