[LLHD][Arc] Indexing and slicing lowering from Verilog to LLVM IR

[AndreyVV-100]

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Hi! I'm trying to use circt for lowering to LLVM IR. I found such a construction in some example:

module Mod (input clk, input a, input b, output logic[1:0] c);
always_ff @(posedge clk) begin
    c[0] <= a;
    c[1] <= b;
end
endmodule

I used this pipeline:

circt-verilog ranges.sv | circt-opt --llhd-early-code-motion --llhd-temporal-code-motion --llhd-desequentialize --llhd-sig2reg --canonicalize | arcilator

But I got error body contains non-pure operation in arcilator. Also I had same error when I tried to use slicing instead of indexing. What needs to be done to run arcilator successfully?