[Seq] Add a new pass to sink clock_gate ops to the users

[prithayan]

This is a new pass that sinks seq.clock_gate into its users and attempts to remove as many seq.clock_gate ops as possible.

Any operation that can potentially encode the enable directly, will replace its gated clock with the un-gated clock and encode the clock gate enable as the operation's enable signal. Currently only the CompRegOp operation is handled, but similar transformation needs to be attempted on other supported operations also.

The first phase of the pass is a global transformation that continues to push the clock gates into the referenced modules, until none of the instance ops are driven by a gated clock. Next, best effort is made to remove the gated clock and encode the enable directly into the operation that is being driven by the clock.

[uenoku]

And if one of the instances has a clock gate in front and the other does not?

Yeah I think this transformation requires fixed-point analysis whose lattice is a pair of clock and enable.

[prithayan]

Thanks a lot @fabianschuiki and @uenoku for the feedback. The major issue in the previous iteration was multiple instances. I have handled that in this version. The other concern regarding the precision of this analysis, this is intended as a fast/simple and best-effort analysis, so its okay to miss a few clock_gates. We donot intend to eliminate all the clock gates. Additionally clock_gates to some public-modules/extern-modules cannot be removed. As Hideto suggested, I am also working on a fixed-point analysis that we might utilize if the need for it arises.

Please take another look at it.