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[FIRRTL] Output directory control for layers and modules

Open rwy7 opened this issue 1 year ago • 2 comments

Add output directory control for layers and firrtl.

For specifying the output directories:

  • Add a new annotation called "circt.OutputDirAnnotation", for specifying the output directory of modules
  • For layers, add syntax for optionally specifying the output directory

In the Lower-Layers Pass:

  • Place layer collateral (the bindfile, any layerblocks->modules) under the output directory of the layer, if there is any.
  • Stop outputting layer collateral under the testbench/views

Add a new pass, AssignOutputDirs, which will sink modules into the output directories they are instantiated from. This pass runs after lower-layers. In conjunction with the changes to the lower-layers pass, this means that modules which are only used under a particular layer will be sunk into that layer's output directory.

rwy7 avatar Apr 30 '24 19:04 rwy7

What is an expected behavior when modules with different output dir annotations are deduplicated?

uenoku avatar May 01 '24 01:05 uenoku

What is an expected behavior when modules with different output dir annotations are deduplicated?

Hey, thanks for taking a look! Two modules will dedup iff they have the same output directory annotation (modulo dirname canonicalization when constructing the the hw::OutputFileAttr). I've added a test for this here.

rwy7 avatar May 06 '24 19:05 rwy7

☝️ After discussing with @darthscsi more about this. This comment is saying that we can remove the OutputDirPrecedenceAnnotation and any logic associated with it and instead compute the LCA based on the LCA of the directories themselves. E.g., SimpleLCA("verilog/design/", "verilog/testbench/") == "verilog/". This cannot express certain things like we do internally where AnnoyingLCA("verilog/design/", "verilog/testbench/") == "verilog/design/"). However, we can change this internally so that we can use the SimpleLCA computation.

Edit: We may be able to get the same behavior as we have today for SimpleLCA by always choosing the provided output directory ("verilog/design/") if the LCA is above the provided output directory.

seldridge avatar Jun 07 '24 19:06 seldridge

Thanks everyone!

rwy7 avatar Jun 14 '24 18:06 rwy7